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Unformatted text preview: Page 327 The I/O Subsystem Chapter Seven 7.1 Chapter Overview A typical program does three basic activities: input, computation, and output. In this section we will discuss the other two activities beyond computation: input and output or I/O. This chapter concentrates on low-level CPU I/O rather than high level file or character I/O. This chapter discusses how the CPU transfers bytes of data to and from the outside world. This chapter discusses the mechanisms and performance issues behind the I/O. 7.2 Connecting a CPU to the Outside World Most I/O devices interface to the CPU in a fashion quite similar to memory . Indeed, many devices appear to the CPU as though they were memory devices. T o output data to the outside world the CPU simply stores data into a "memory" location and the data magically appears on some connectors external to the computer . Simi- larly , to input data from some external device, the CPU simply transfers data from a "memory" location into the CPU; this "memory" location holds the value found on the pins of some external connector . An output port is a device that looks like a memory cell to the computer but contains connections to the out- side world. An I/O port typically uses a latch rather than a flip-flop to implement the memory cell. When the CPU writes to the address associated with the latch, the latch device captures the data and makes it available on a set of wires external to the CPU and memory system (see Figure 7.1 ). Note that output ports can be write-only , or read/write. The port in Figure 7.1 , for example, is a write-only port. Since the outputs on the latch do not loop back to the CPU s data bus, the CPU cannot read the data the latch contains. Both the address decode and write control lines must be active for the latch to operate; when reading from the latch s address the decode line is active, but the write control line is not. Figure 7.1 A Typical Output Port Figure 7.2 shows how to create a read/write input/output port. The data written to the output port loops back to a transparent latch. Whenever the CPU reads the decoded address the read and decode lines are active and this activates the lower latch. This places the data previously written to the output port on the CPU s data bus, allow- ing the CPU to read that data. A read-only (input) port is simply the lower half of Figure 7.2 ; the system ignores any data written to an input port. Data Bus from CPU L a t c h CPU write control line Address decode line W En Data Data to outside world Page 328 Figure 7.2 An Output Port that Supports Read/Write Access Note that the port in Figure 7.2 is not an input port. Although the CPU can read this data, this port or ganiza- tion simply lets the CPU read the data it previously wrote to the port. The data appearing on an external connec- tor is an output port (only). One could create a (read-only) input port by using the lower half of the circuit in Figure 7.2 . The input to the latch would appear on the CPU s data bus whenever the CPU reads the latch data.s data bus whenever the CPU reads the latch data....
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This note was uploaded on 08/08/2011 for the course CS 101 taught by Professor Jitenderkumarchhabra during the Summer '11 term at National Institute of Technology, Calicut.
- Summer '11