MemoryArchitecture - Memory Architecture Memory...

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Memory Architecture Beta Draft - Do not distribute © 2001, By Randall Hyde Page 303 Memor y Architecture Chapter Six 6.1 Chapter Overview This chapter discusses the memory hierarch y – the dif ferent types and performance le v els of memory found on a typical 80x86 computer system. Man y programmers tend to vie w memory as this big neb ulous block of storage that holds v alues for future use. From a semantic point of vie w , this is a reasonable vie w . Ho we v er , from a performance point of vie w there are man y dif ferent kinds of memory and using the wrong one or using one form improperly can ha v e a dramatically ne g ati v e impact on the performance of a program. This chapter discusses the memory hierarch y and ho w to best use it within your programs. 6.2 The Memory Hierarchy Most modern programs can benefi t greatly from a lar ge amount of v ery f ast memory . A ph ysical reality , ho we v er , is that as a memory de vice gets lar ger , it tends to get slo wer . F or e xample, cache memories (see “Cache Memory” on page 153 ) are v ery f ast b ut are also small and e xpensi v e. Main memory is ine xpensi v e and lar ge, b ut is slo w (requiring w ait states, see “W ait States” on page 151 ). The memory hierarch y is a mechanism of comparing the cost and performance of the v arious places we can store data and instructions. Figure 6.1 pro vides a look at one possible form of the memory hierarch y . Figure 6.1 The Memory Hierarchy At the top le v el of the memory hierarch y are the CPU’ s general purpose re gisters. The re gisters pro vide the f astest access to data possible on the 80x86 CPU. The re gister fi le is also the smallest memory object in the memory hierarch y (with just eight general purpose re gisters a v ailable). By virtue of the f act that it is vir - tually impossible to add more re gisters to the 80x86, re gisters are also the most e xpensi v e memory locations. Increasing Cost, Increasing Speed, Decreasing Size. Decreasing Cost, Decreasing Speed, Increasing Size. Registers Level One Cache Level Two Cache Main Memory NUMA Virtual Memory Near-Line Storage Off-Line Storage Hard Copy File Storage Network Storage
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Chapter Six Volume Two Page 304 © 2001, By Randall Hyde Beta Draft - Do not distribute Note that we can include FPU, MMX, SIMD, and other CPU re gisters in this class as well. These additional re gisters do not change the f act that there are a v ery limited number of re gisters and the cost per byte is quite high (fi guring the cost of the CPU di vided by the number of bytes of re gister a v ailable). W orking our w ay do wn, the Le v el One Cache system is the ne xt highest performance subsystem in the memory hierarch y . On the 80x86 CPUs, the Le v el One Cache is pro vided on-chip by Intel and cannot be e xpanded. The size is usually quite small (typically between 4Kbytes and 32Kbytes), though much lar ger than the re gisters a v ailable on the CPU chip. Although the Le v el One Cache size is fi x ed on the CPU and you cannot e xpand it, the cost per byte of cache memory is much lo
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MemoryArchitecture - Memory Architecture Memory...

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