V2Questions - Questions, Projects, and Laboratory Exercises...

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Questions, Projects, and Laboratory Exercises Beta Draft - Do not distribute © 2001, By Randall Hyde Page 355 Questions, Projects, and Labs Chapter Eight 8.1 Questions 1. What three components make up Von Neumann Machines? 2. What is the purpose of a) The system bus b) The address bus c) The data bus d) The control bus 3. Which bus defines the “size” of the processor? 4. Which bus controls how much memory you can have? 5. Does the size of the data bus control the maximum value the CPU can process? Explain. 6. What are the data bus sizes of: a) 8088 b) 8086 c) 80286 d) 80386sx e) 80386 f) 80486 g)Pentium h) Pentium II 7. What are the address bus sizes of the above processors? 8. How many “banks” of memory do each of the above processors have? 9. Explain how to store a word in byte addressable memory (that is, at what addresses). Explain how to store a double word. 10. How many memory operations will it take to read a word from the following addresses on the following pro- cessors? 11. Repeat the above for double words T able 16: Memory Cycles for Word Accesses $100 $101 $102 $103 $104 $105 8088 80286 80386 T able 17: Memory Cycles for Doubleword Accesses $100 $101 $102 $103 $104 $105 8088
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Chapter Eight Volume Two Page 356 © 2001, By Randall Hyde Beta Draft - Do not distribute 12. Explain which addresses are best for byte, word, and doubleword variables on an 8088, 80286, and 80386 processor. 13. Given the system bus size, what address boundary is best for a real64 object in memory? 14. What is the purpose of the system clock? 15. What is a clock cycle? 16. What is the relationship between clock frequency and the clock period? 17. Explain why 10ns memory should not work on a 500 MHz Pentium III processor? Explain why it does. 18. What does the term “memory access time” mean? 19. What is a wait state? 20. If you are running an 80486 at the following clock speeds, how many wait states are required if you are using 80ns RAM (assuming no other delays)? a) 20 MHz b) 25 MHz c) 33 MHz d) 50 MHz e) 100 MHz 21. If your CPU runs at 50 MHz, 20ns RAM probably won’t be fast enough to operate at zero wait states. Explain why. 22. Since sub-10ns RAM is available, why aren’t most systems zero wait state systems? 23. Explain how the cache operates to save some wait states. 24. What is the difference between spatial and temporal locality of reference? 25. Explain where temporal and spatial locality of reference occur in the following Pascal code: while i < 10 do begin x := x * i; i := i + 1; end; 26. How does cache memory improve the performance of a section of code exhibiting spatial locality of refer- ence? 27. Under what circumstances is a cache not going to save you any wait states? 28. What is the effective (average) number of wait states the following systems will operate under? a) 80% cache hit ratio, 10 wait states (WS) for memory, 0 WS for cache. b) 90% cache hit ratio; 7 WS for memory; 0 WS for cache. c) 95% cache hit ratio; 10 WS memory; 1 WS cache.
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V2Questions - Questions, Projects, and Laboratory Exercises...

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