appendix_a

appendix_a - Appendix A: Hardware Description Language...

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Appendix A: Hardware Description Language (HDL) Intelligence is the faculty of making artiFcial objects, especially tools to make tools. —Henry Bergson (1859–1941) A Hardware Description Language (HDL) is a formalism for deFning and testing chips : objects whose interfaces consist of input and output pins that carry Boolean signals, and whose bodies are composed of interconnected collections of other, lower-level, chips. This appendix describes a typical HDL, as understood by the hardware simulator supplied with the book. Chapter 1 (in particular, section 1.1) provides essential background without which this appendix does not make much sense. How to Use This Appendix This is a technical reference, and thus there is no need to read it from beginning to end. Instead, we recommended focusing on selected sections, as needed. Also, HDL is an intuitive and self-explanatory language, and the best way to learn it is to play with some HDL programs using the supplied hardware simulator. Therefore, we recommend to start experimenting with HDL programs as soon as you can, beginning with the following example. A.1 Example ±igure A.1 speciFes a chip that accepts two three-bit numbers and outputs whether they are equal or not. The chip logic uses Xor gates to compare the three bit-pairs, and outputs true if all the comparisons agree. Each internal part Xxx invoked by an HDL program refers to a stand-alone chip deFned in a separate Xxx.hdl program. Thus the chip designer who wrote the EQ3.hdl program assumed the availability of three other lower-level programs: Xor.hdl , Or.hdl , and Not.hdl . Importantly,
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though, the designer need not worry about how these chips are implemented. When building a new chip in HDL, the internal parts that participate in the design are always viewed as black boxes, allowing the designer to focus only on their proper arrangement in the current chip architecture. Thanks to this modularity, all HDL programs, including those that describe high-level chips, can be kept short and readable. For example, a complex chip like RAM16K can be implemented using a few internal parts (e.g., RAM4K chips), each described in a single HDL line. When fully evaluated by the hardware simulator all the way down the recursive chip hierarchy, these internal parts are expanded into many thousands of interconnected elementary logic gates. Yet the chip designer need not be concerned by this complexity, and can focus instead only on the chip’s top- most architecture. A.2 Conventions File extension: Each chip is de±ned in a separate text ±le. A chip whose name is Xxx is de±ned in ±le Xxx.hdl . Chip structure: A chip de±nition consists of a header and a body . The header speci±es the chip interface , and the body its implementation . The header acts as the chip’s API, or public documentation. The body should not interest people who use the chip as an internal part in other chip de±nitions.
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appendix_a - Appendix A: Hardware Description Language...

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