Ve312_Homework+3

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Unformatted text preview: University of Michigan‐Shanghai Jiao‐Tong University Joint Institute Ve312: Digital Integrated Circuits Homework 3 (Lab‐Based)(Due: 10/25/2010) Source: Certificate Program in Integrated‐Circuit Design and Techniques University of California, Berkeley Extension Note: In this lab, you will be asked to use HPSICE to perform simulation of MOSFET with an industrial level process library. Try to analyze the simulation results according to what you’ve learned from textbooks and figure out the difference between the idea hand‐calculation model and the complex one. The environment and references are described as follows: HSPICE 2005 Library File: log018.l, the TSMC 0.18um technology library References are listed at the end of the document 1. MOSFET—HSPICE Simulation and Reasoning HSPICE Simulation: (a), (b) Reading & physical explanation: (c) Reasoning: (d) *Modeling: (e) (Optional. Bonus will be given if you do it.) For the MOSFET circuit shown, 2 1 M1 vDS vGS M1 is an NMOSFET using the model NCH in the lib log018.l. (a) Assume the width of M1 is 1µm, the length is 0.18µm, use HSPICE to simulate the ID vs. VDS characteristic for various VGS. Use Avanwaves to check the ID curve and record the screenshot in your report. Hint: Use .DC and SWEEP to sweep VDS from 0V to 3V with VGS varying from 0V to 3V incrementing every 0.5V. .dc vds 0 1.8 0.05 sweep vgs 0 1.8 0.3 Use the following sentence to specify the lib .lib 'log018.l' tt *tt means typical [Ve312: Digital Integrated Circuits Homework 3] Page 1 (b) Keep the ratio W/L the same while enlarging the width and the length to 1µm and 0.5µm respectively. Re‐simulate the ID vs. VDS characteristic for various VGS. Use AvanWaves to check the ID curve and record the screenshot in your report. (c) Reading Assignment: Explain the velocity saturation effect in a short‐channel MOSFET. References: [1] S. M. Sze, “Semiconductor Devices, Physics and Technology,” New York: Wiley, 2002. [2] Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, 1998. [3] Jan. M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A Design Perspective,” Prentice Hall, Inc., 2003. (d) Compare the results you got in (a) and (b). Is there any difference? Try to explain it. Hint: Channel Length Modulation and Velocity Saturation (e) For digital switching circuits, especially if you need only a “qualitative” simulation of the timing and the function, LEVEL 1 run‐time can be about half that of a simulation using the LEVEL 2 model. The agreement in timing is approximately 10%. The LEVEL 1 model, however, results in severe inaccuracies in DC transfer functions of any TTL‐compatible input buffers in the circuit [2]. Try to use LEVEL 1 SPICE model, which is based on the square law, to approximate the complex model you used in (b). HINT: The three most important parameters of LEVEL 1 MOSFET are KP, LAMDA and VTO since we use the following equations at LEVEL 1. Cutoff Region, VGS≤Vth iDS = 0 Linear (Triode) Region, VDS < VGS‐Vth i DS = KP Weff Leff (1 + LAMBDA • v DS )[vGS − Vth − v DSv DS 2 Saturation Region, VDS ≥ VGS‐Vth iDS = KP Weff Leff (1 + LAMBDA • vDS )(vGS − Vth ) 2 So we may use the following way to approximate the complex model (Youare encouraged to use your own method as long as you can get a good approximation): Use .OP to print out the operation point (set VDS=VGS=0.9V to keep the transistor saturate) [Ve312: Digital Integrated Circuits Homework 3] Page 2 Read VTO and ID in the corresponding *.lis file. Use measure tool to obtain the derivative of ID over VDS (i.e., GDS). Then use the approximate equation GDS=ID*LAMBDA to calculate the value of LAMBDA. Use the equations to calculate KP inversely. [Ve312: Digital Integrated Circuits Homework 3] Page 3 ...
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