h62de2 0506 exam - H620E2-E1! l l The University of...

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Unformatted text preview: H620E2-E1! l l The University of Nottingham SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING A LEVEL 2 MODULE, SPRING SEMESTER 2005-2006 DIGITAL ELECTRONICS 2 Time allowed TWO Hours Candidates must NOT start writing their answers until told to do so Answer ALL questions in section A and ONE question from section B Marks awarded for sections of questions are shown in brackets after the relevant section. Only silent, self contained calculators with a Single—Line Display, or Dual-Line Display are permitted in this examination. Dictionaries are not allowed with one exception. Those whose first language is not English may use a standard translation dictionary to translate between that language and English provided that neither language is the subject of this examination. Subject specific translation dictionaries are not permitted. No electronic devices capable of storing and retrieving text, including electronic dictionaries, ‘ may be used. ‘ DO NOT turn over examination paper until instructed to do so. ADDITIONAL MATERIAL: ‘ The following data sheets are enclosed with the examination paper. These contain information that is necessary to answer some of the questions in this paper. You are advised 3 to familiarise yourself with this material before attempting any of the questions: Handout 1 Handout 2 The following logic diagram associated with Handout 2 is also enclosed: Handout 2A H62DE2-E1 ‘ Turn over‘ 2 HGZDEZ-El SECTION A Attempt ALL the questions from this section. You are advised to spend about 80 minutes on this section. 1 Determine and state the logic function represented by the CMOS circuit in Figure Q1. ‘ [5 marks] Vdd l l l l Figure Q1 2 (a) Explain the difference between static power dissipation and dynamic power I dissipation in logic circuits. [2 marks] (b) Calculate the dynamic power dissipated by a CMOS inverter operated from a 5V power supply driving a 50 pF load at the following clock frequencies: i) 20 kHz [1 mark] ii) 5 MHz [1 mark] 3 A digital circuit is defined by Y = Z(0,l,2,8,11)+ d(3,9,15) Using the Quine-McCluskey technique, write out List 1 and derive List 2 from List 1. [3 marks] H62DE2-E1 3 ' HGZDEZ-Ell 4 The circuit shown in Figure Q4 shows part of a digital circuit. The circuit is to be implemented using CMOS 74LVC logic gates operating from a 3.5 V supply at a temperature of 25 degrees centigrade. i Figure Q4 From the data sheets provided, calculate the following: (a) The noise margin at point p when that point is at logic 0. [1 mark]1 (h) The noise margin at point p when that point is at logic 1. [1 mark] (c) The maximum propagation delay for the circuit shown. [1 mark]l 5 I Explain the difference between the Mealy and Moore approaches in synchronous sequential circuit design. [2 marks] 6 A state table has been derived for a particular problem as follows: ; Present State Next State Outut Z 0 — x=1 —_ —_ —- (a) Remove any redundant states and draw the reduced state table. [3 marij (b) Draw the state diagram for your answer to part (a). [2 markst (c) State with reasons how many flip-flops are required for the implementation of the l reduced state diagram in part (b). [1 mark] H62DE2-E1 Turn Over 4 H62DE2-Ei 7 Some VHDL code is presented below: 3 library IEEE; use IEEE.std_logic_1164.all; entity TOSOZB is port ( A: in STD_LOGIC; B: in STD_LOGIC; C: in STD_LOGIC; F: out STD_LOGIC ); end TOBOZB; architecture T08023_arch of TOBOZB is component and2 ! port(IO,11:in STD_LOGIC; 0: out STD_LOGIC); end component; component or2 port(IO,11:in STD_LOGIC; 0: out STD_LOGIC); end component; signal D : STD_LOGIC; begin 1 GATE1:or2 port map(B,C,D); GATE2:and2 port map(A,D,F); end T08023_arch; (a) State whether this is a behavioural or a structural description of the circuit. [1 mark] (b) Draw the circuit represented by this code indicating external and internal signals. [3 marks] 8 For each of the following types of memory, draw a diagram showing how data are stored i) EPROM. [2 marks] ii) SRAM. [2 marks] iii) DRAM. [2 marks] 9 State one advantage and one disadvantage of using a Field Programmable Gate Array (FPGA) in electronic design compared with using a Mask Programmable Gate Array (MPGA). [2 marks] H62DE2-E1 5 H62DE2-E11 10 A 4—bit Look Ahead Carry Adder is illustrated in Figure Q10: 1 X3 Y3 X2 Y2 X1 Y1 X0 Y0 Figure Q10 The relation between the Carry-Out from adder i, CH1 and the carry in to adder i, C. given by Cm = XIYI +XICI +YICI (a) Show that the carry-out from FAl can be written directly in terms of X0, Y0, Xland Y1 as follows: C2=X1YI+XOY0(X1+YI) * [3 marks] (b) State one advantage and one disadvantage of using a Look Ahead Carry Adder 1 compared with a Ripple Carry Adder. [2 marks] H62DE2-E1 Turn Over 6 H62DE2-E1 SECTION B Attempt ONE question from this section. You are advised to spend about 40 minutes on this section 11 It is required to design a digital circuit to detect at least two consecutive 1’s in a sequence of four bits. (a) Design an iterative circuit to achieve this requirement showing: i) The logic circuit for each cell. [15 marks] ii) The output circuit. [4 marks] (b) Indicate how you would modify your design to detect at least two consecutive 1's l in a sequence of eight bits. [1 mark]1 12 It is required to design a digital circuit to count down in binary from 7 to 0. When the : counter reaches 0 it stays at 0. X is an external input. IfX = 0 then the counter counts i down as normal. If X = 1 then the count is frozen to its present value. - a) Design an appropriate digital circuit using positive edge triggered D-type flip flops. 1 [10 marks] b) You are required to implement this counter using the 16V8PAL for which a logic diagram and data sheet are provided. i) 0n the logic diagram show the switching matrix interconnections required to implement your design. [6 marks] ii) Determine and state the values of SLO," SL1," $60 and SG1 that are necessary to give the correct configuration of each macrocell. [4 marks] 13 A thermometer is attached to the outside of a refrigerator. You have built some circuitry to convert the analogue measurement of the room temperature to a 5-bit binary number representing the temperature to the nearest degree centigrade; for example 11000 I represents 24 degrees centigrade. If the temperature is greater than 31 degrees i centigrade, then the digital reading is 11111. If the temperature falls below zero, then ' the digital reading is 00000. The refrigerator is designed to operate at room temperatures between 5 degrees 1 centigrade and 27 degrees centigrade inclusively. 1 You are required to design a digital circuit, for which the 5-bit binary representation of temperature is the input, and the output is to an alarm that should be sounded if the temperature measurement falls outside the accepted limits for correct operation of the refrigerator. Design the required circuit. [20 marks] H620E2-E1 End 1,19me l HbZDEZ -—€' SN54LVCO2A, SN74LVC02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCASZBOM — JANUARY 1993 - REVISED SEPTEMBER 2002 I Operate From 1.65 V to 3.6 V 0 Latch-Up Performance Exceeds 250 mA Per 0 Inputs Accept Voltages to 5.5 V JESD 17 . Max tpd o1:4'4 "5 at 3_3 V O ESD Protection Exceeds JESD 22 0 Typical VOLp (Output Ground Bounce) — gggoQVMHuman'BogylMXde' (MM-A) <0.8 v at vcc = 3.3 v TA = 25°C " ' 3° "‘9 M° e ( "5"" . ' — 1000-V Charged-Device Model (c101) Typical VOHV (Output VOH Undershoot) >2 V at Vcc = 3.3 V, TA = 25°C SN54chozA . . . J OR w PACKAGE SN74ch02A . . . RGY PACKAGE (TOP VIEW) SNMLVCOZA . . . FK PACKAGE SN74LVCOZA . . . D, DB. NS. OR PW PACKAGE (TOP VIEW) (TOP VIEW) D Z 0 NC — No intemal connection descriptionlordering Information The SN54LVCOZA quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V Vcc operation. and the SN74LVCOZA quadruple 2-Input positive-NOR gate is designed for 1.65—V to 3.6~V VCC operation. The 'LVCOZA devices perform the Boolean function Y = A + B or Y = K v E in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. TOP-SIDE MARKING LCOZA ORDERING INFORMATION PART NUMBER swmvcozmeva SN74LVCOZAD SNT4choonR SN‘MLVCOZANSR SN74LV002ADBR SN‘MLVCOZAPWR TSSOP—PW swsawcow SNJ54LVC02AW SNJ54LVCOZAW coup — J -55°c to 125°C CFP - w Lccc - FK SNJ54LVC02AFK SNJ54LVCOZAFK T Package drawings. standard packing quantities. thermal date. symbolization. and PCB design guidelines are available at www.ti.comlsclpackage. —40°_c to 85°C SSOP - DB r. 5 O i SNJ54LVCOZAJ Please be aware that an important notice concerning availability. standard warranty, and use In critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ‘9 TEXAS INSTRUMENTS POST OFFICE BOX 655303 0 DALLAS. TEXAS 75265 1 A PRODUCTION DATA information In until u of Ilcltlon date. Wounmwlpoclflcltlomwlhotlnmol Imhlh’lllmfll mndardmmtymmduclmmuhg do" notnccuurlly Include utthgoilllpmmm Copyright 0 2002. Texas Instruments incorporated 0n product: min-ate IIIIL-PRF-usas. III minor: m lama mien chemise noted. On Ill other products. production pros-ulna am not nan-wily hctudu touting oi Ill perms SN54LVCOZA, SN74LVC02A ., QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCASZBOM - JANUARY 1993 - REVISED SEPTEMBER 2002 FUNCTION TABLE (each gate) logic diagram, each gate (positive logic) ::Do——v absolute maximum ratings over operating free-air temperature range (unless otherwise noted)’r Supply-voltage range, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 6.5 V Input-voltage range. V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . —O.5 V to 6.5 V ‘ Output-voltage range. V0 (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . —0.5 V to Vcc + 0.5 V ; input clamp current. llK (V. < 0) . . . . . . . . . . . .; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current. IOK (V0 < 0) . . . . . . . . . . . . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA 1 Continuous output current. lo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA ? Continuous current through Vcc or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i100 mA Package thermal impedance. 9M (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . .. 86°CIW (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 96°CIW (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°CIW (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°CIW (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°CIW Storage temperature range. Tstg . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. —65°C to 150°C 1‘ Stresses beyond those listed under'absolute maximum ratings“ may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other conditions beyond those Indicated under “recommended operating conditions“ is not implied. Exposure to ebsolute-maxlmum—rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2 2. The value of vcc Is provided In the recommended operating conditions table. ' 3. The package thermal impedance ls calculated in accordance with JESD 51-7. - 4. The package thermal impedance is calculated In accordance with JESD 51 -5. *9 TEXAS INSTRUMENTS 2 POST OFFICE BOX 855303 . DALLAS. TEXAS 75265 SN54LVCOZA, SN74LVC02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCASZBOM — JANUARY 1993 — REVISED SEPTEMBER 2002 recommended operating condltlons (see Note 5) VJH High-level input voltage VIL Low-level input voltage V; Input voltage V0 Output voltage IQH High-level output current l IOL Low-level output current I 3 TA Operating free-air temperature NOTE 5: All unused Inputs of the device must be held at Vcc or GND to ensure proper devloe operatic Implications of Slow or Floating CMOS Inputs, literature number SCBAOM. n. Refer to the 11 appllcation report. 4:? TEXAS INSTRUMENTS l POST OFFICE BOX 655303 . DALLAS. TEXAS 75265 3 SN54LVC02A, SN74LVCO2A ‘ V QUADRUPLE 2-lNPUT POSITIVE-NOR GATES SCASZBOM - JANUARY 1993 — REVISED SEPTEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) IOH =-12 mA IO“ = —24 mA 1 I “on 1.65Vto3.6V 0'- "A 2.7 v to 3.6 v i I0L=4mA 1' All typii values are at vcc = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC02A FROM TO Vcc I 3.3 V “mm (m, (OW m switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM TO —- operating characteristics, TA = 25°C TEST Vcc 31.8 V Vcc I 2.5 V vcc I 3.3 V “WEE” comm *9 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 . DALLAS. TEXAS 75265 Pugh/90ml? HBZDEz—El PALCE16V8 COM'L:H-5/7l10l15l25, Q-10I15/25 IND:H-10/25, Q-20I25 PALCE16V82 COM'L:-25 lND:-12!15/25 PALCE16V8 and PALCE16V82 Families EE CMOS (Zero-Power) 20-Pin Universal Programmable Array Logic . ' gamma DISTINCTIVE CHARACTERISTICS 9 Pin and function compatible with all 20-pin PAL” devices _ 9 Electrically erasable CMOS technology provides reconfigurable logic and full testability 9 High-speed CMOS technology — 5-ns propagation delay for version — 7.5-ns propagation delay for "-7" version Direct plug-in replacement for the PAL16R8 series Outputs programmable as registered or combinatorial in any combination Peripheral Component Interconnect (PCI) compliant Programmable output polarity Programmable enable/disable control Preloadable output registers for testability Automatic register reset on power up Cost-effective 20-pin plastic DIP, PLCC, and 80K: packages Extensive third-party software and programmer support Fully tested for 100% programming andfunctional yields and high reliability 5-ns version utilizes a split leadframe for improved performance a!” ............ GENERAL DESCRIPTION The PALCE16V8 is an advanced PAL device built with low-power, high-speed. electrically- erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8. with the exception of the PAL16C1. The PALCEIGVBZ provides zero standby power and high speed. At 30-pA maximum standby current. the PALCEIBVSZ allows battery-powered operation for an extended period. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form. taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active—high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. ————--—————___.—__—.._.__—__ Publication! 16193 Rev:E Amendment/0 Issue Date: Navelnber 1998 BLOCK DIAGRAM Programmable AND Array 32x64 ! MACRO MACRO MACRO - 4 < d 4 M60 - _ _ I I MACRO MACR MACRO MAC ma - <— — Mae ‘— M67 II II II II I II t“ I" i‘ t‘ h“ 0 R0 4 1 I II r 16493E-1 FUNCTIONAL DESCRIPTION The PALCEIBVB is a universal PAL device. The PALCEIBVSZ is the zero-power version of the PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. It has eight independently configurable macrocells (MCo-MC7). Each macrocell can be configured as registered output, combinatorial output. combinatorial 1/0 or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user- programmable input 51 nal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE). respectively. for all flip~flops. Unused input pins should be tied directly to Vcc or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE16V8 are automatically configured from the user's design specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file. once downloaded to a programmer. configures the device according to the user's desired function. The user is given two design options with the PALCEIBVB. First. it can be programmed as a standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply device codes for. the standard PAL device architectures to be used with the PALCEIBVB. The programmer will program the PALCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. 2 PALCE16V8 and PALCE16VBZ Families iggtawfiice Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell. To Adjacent Macrocell — I = SL1x CLK > 1 0 ‘ _ 1 1 . O X From 'so1 $1.0x 931369” ‘In macrocell.: M00 and M67, SC! is replaced by???) on the feedback multiplexer: 1 649352 Figure 1. PALCE16V8 Macroceli CONFIGURATION OPTIONS Each macrocell can be configured as one of the following: registered output. combinatorial output, combinatorial 1/9; or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration. it is always disabled. With the exception of MCo and M0,. a macrocell configured as a dedicated input derives the input signal from an adjacent I/O. MCO derives its input from pin 11 m) and MC7 from pin 1 (CLK). The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SGO and 5G1) and 16 local bits (SLOO through SL07 and SLlo through SL17). SGO determines whether registers will be allowed. SGl determines whether the PALCE16V8 will emulate a PAL16R8 family or a PALlOI-IB family device. Within each macrocell, SLO,“ in conjunction with SCI, selects the configuration of the macrocell, and SLIx sets the output as either active low or active high for the individual macrocell. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input. an enable select, an output select, and a feedback selectiultiplexer. SCI and SL0x are the control signals for all four multiplexers. In MCo and M0,, 860 replaces SG_i on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC7 and OE the adjacent pin for MCO. PALCE16V8 and PALCE16V82 Families 3 iiiagiw Registered Output Configuration The control bit settings are SGO = 0, SGl = l and SLUx = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined bySle' The flip-flop is loaded on the LOW—to—HIGH Ensition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE16V8 has three combinatorial output configurations: dedicated output in a non- registered device, 1/0 in a non-registered device and 1/0 in a registered device. Dedicated Output in a Non-Registered Device The control bit settings are 3G0 = 1. SC] = 0 and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the excepfion of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the feedback path of M0,. and pin 11 will use the feedback path of MCO. Combinatorial HQ in a Non-Registered Device The control bit settings are SGO = l, 561 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Because CLK and m are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of M0,, and pin 11 will use the feedback path of MCO. Combinatorial l/O in a Registered Device The control bit settings are SGO = O. SGI = l and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding [/0 signal. Dedicated Input Configuration The control bit settings are 3G0 -~ 1, 8G] = O and SL0x = l. The output buffer is disabled. Except for MCO and MC7. the feedback signal is an adjacent I/O. For MCO and M0,. the feedback signals are pins 1 and 11.‘ These configurations are summarized in Table l and illustrated in Figure 2. ‘ Table ‘i. Macrocell Confi - uration Cell Devices Cell Devices SLOX Configuration Emulated Configuration Emulated Device Uses Registers Device Uses No Registers 14H4. IGHZ. 10l8. Registered Output Pfllfii 416% cm???“ " P“ ms. nu. 161.2 Combinatorial PM] 2H6. 141'“. PALISRG. 16!“ mm, 121.6, 14”. U0 ISLZ Combinatorial PALIOH8. 12H6. 4 ' PALCE16V8 and PALCE16V82 Families iéétawfiiw Programmable Output Polarity The polarity of each macrocell can be active-high or active-low. either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted). and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is through a programmable bit Sle which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if Sle is 1 and active low if Sle is D. PALCE1 6V8 and PALCE16VBZ Families 5 . amulet! c. Combinatorial i/O active low d. Combinatorial [/0 active high Vcc VCC 1 Note 1 Note 1 e. Combinatorial output active low f. Combinatorial output active high 3 Notes: 1. Feedback Is not available on pm: 15 and 16111 the Kl—G Adjacent IIO pin combinatorial output mode. Note 2 2. This configuration ls not available on pins 15 and I 6. 9. Dedicated input . _ 16493E-2 Figure 2. Macrocell Configurations 6 PALCE‘ISVB and PALCE16VBZ Families team..ch Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCEIGVB will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition. transitions from illegal states can be verified by loading illegal statesand observing proper recovery. Security Bit A security bit is provided on the PALCEIBVB as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE16V8 offers a very high level of built-in quality. The e’rasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post—programming functional yields in the industry. Technology The high-speed PALCE16V8 is fabricated with Vantis' advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with 'ITL devices. This technology provides strong input clamp diodes, output slew-rate control. and a grounded substrate for clean switching. PCI Compliance PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCElBVB's predictable timing ensures compliance with the PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCEIGVSZ features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 us). the PALCEIGVSZ will go into standby mode. shutting down PALCE16V8 and PALCE16V82 Families 1 " Wm most of its internal circuitry. The current will go to almost zero (ICC < 15 11A). The outputs will 1 maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input switches. the internal circuitry is fully enabled. and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. This saving is illustrated in the ICC vs. frequency graph. Product-Term Disable On a programmed PALCElBVBZ, any product terms that are not used are disabled. Power is cut off from the product terms so that they do not draw current. As shown in the ICC vs. frequency 1 graph. product-term disabling results in considerable power savings. This saving is greater at the ‘ higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Po wer PLDs. 8 PALCE1BV8 and PALCE16VBZ Families LOGIC DIAGRAM 158193 1 I ‘ 4 . 1 1 O as: ===a=====aaaasaasaasaaassaai— i 7 :::=========================fl= I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII 1 2] pr -III-lII-lll—lll-III-III-llI , I I-lll-ll -III_:— 1 :.. --':::=:: -:::=-—- 15 ===-III-III-:====:l-lIl-lll-:=:=E= IIIII IIIIIIIIIIIIIIIIIIII II I l-III-III-III_III-III-III—‘ .- 15 III-I '3 n fi-IIl-III-I l-III III-III-IlI-III_‘ III—III-III-II 23 III-III-III-II 2‘ III—III-Ill-III- II-III-III-III—: 55:=:::=:::=::55 ::=:::=:::=:5§E§-— j 31 EE:=:::=:::=::EE ::=::==:::==EEE§= ? IIIIIIIIIIIII II IIIIIIIIIIIIII ' l‘ E p--------—---- - II-IlI-lll-III—‘ 0 34 7! 11121516 192023242'i28 31 autos 1 6493E-2 PALCE‘IGVB and PALCE‘IBVBZ Families 9 LOGIC DIAGRAM (CONTINUED) 0 3‘ 731112151519202324272831 MOE — ' l l h I I 32 l -- =: *- "0: III-III-III-III-III-III—I I .5 h‘III-III-III-III-I -III-II i ‘0 III—III-III-III-III-III-II III-III-III-III-IIl-III-II m yo; I6 I] h-III—III- Ill-IIl-l -III-III—_d i III “‘3 V01 III-III-III-III-III I .7 [:1 .‘III_IIIHIII-III-III- Il-I -III—‘ i 55 III-III-III-III- I III-III-III-III- III—III-III—III- II-III-III- EM U00 II-III—III— II-III-III- Il—I— I III-III-I-l-I .-----.-._._ a IIIIIIlIIlIIliiiiiiiiilIllllI III-III-II I [a [:1 p-- II —III- II I— I-Ill- 0 34 76111215161920 2324 2728 31 GN‘DE; 16493 E-6 (concluded) 10 PALCE16V8 and PALCE16VBZ Families ...
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This note was uploaded on 08/14/2011 for the course ELECTRONIC H62ELD taught by Professor Professore during the Spring '09 term at Uni. Nottingham.

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h62de2 0506 exam - H620E2-E1! l l The University of...

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