H62ELD 2008-9 - H62ELD-E1 The University of Nottingham...

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Unformatted text preview: H62ELD-E1 The University of Nottingham DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING A LEVEL 2 MODULE, SPRING SEMESTER 2009 ELECTRONIC ENGINEERING Time allowed THREE Hours Candidates may complete the front cover of their answer book and sign their desk card but must NOT write anything else until the start of the examination period is announced. Answer ALL questions from SECTION A and TWO questions from SECTION B . Marks awarded for sections of questions are shown in brackets after the relevant section. Only silent, self contained calculators with a Single-Line Display, or Dual-Line Display are permitted in this examination. Dictionaries are not allowed with one exception. Those whose first language is not English may use a standard translation dictionary to translate between that language and English provided that neither language is the subject of this examination. Subject specific translation dictionaries are not permitted. No electronic devices capable of storing and retrieving text, including electronic dictionaries, may be used. DO NOT turn examination paper over until instructed to do so ADDITIONAL MATERIAL: Handout : Data Sheet on CMOS SN74LV H62ELD-E1 Turn over 2 H62ELD-E1 SECTION A Answer ALL questions in this section. You should spend about an hour and a half on this section. 1. (a) The circuit in Figure Q1(a) represents a Schmitt trigger. The output voltage from the comparator is 10 V. Determine i) The Upper Trigger Point [1 mark] ii) The Lower Trigger Point [1 mark] iii) The Hysteresis. [1 mark] 20 k 8 k Figure Q1(a) (b) In a feedback oscillator, the amplifier is non-inverting and has a gain of A. The amplitude response of the frequency selective circuit is B at the frequency of interest. i) State the condition for oscillations to be sustained in the steady state. [1 mark] ii) State the required phase response of the frequency selective circuit at the frequency of interest. [1 mark] (c) A 3.46 V dc analogue signal is input to a 3-bit Successive Approximation ADC. The maximum analogue voltage V max = 8 V and the clock frequency is 1 MHz. i) Determine the digital output at each clock cycle. [2 marks] ii) Determine how long it takes for the conversion to be carried out.[1 mark] H62ELD-E1 3 H62ELD-E1 (d) A Function Generator is shown in Figure Q1(d)....
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This note was uploaded on 08/14/2011 for the course ELECTRONIC H62ELD taught by Professor Professore during the Spring '09 term at Uni. Nottingham.

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H62ELD 2008-9 - H62ELD-E1 The University of Nottingham...

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