H62ELD Solutions 2008 - H62ELD ELECTRONIC ENGINEERING...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: H62ELD ELECTRONIC ENGINEERING Solutions to Examination 2008 SECTION A 1 (a) 6 10 100 . 10 10 = + = + = R V R V MAX UTP [1] Hence R = 6.67 k Ω [1] (b) V out = V MAX , Hence reference voltage MAX r V R R R V . 2 1 1 + = Capacitor charges up until V- = V r in which case V out switches to – V MAX and MAX r V R R R V . 2 1 1 +- = [1] Capacitor discharges until V- = V r in which case V out = V MAX again and the output from the comparator is a square wave. [1] (c) i) Noise is broadband (white noise) and is input to the frequency selective network. The output from this network will be a sine wave of the required frequency. [1] ii) AB > 1. [1] (d) Total number of comparators = 2 16-1 2 ≈ 16 . Hence total power dissipated = 2 16 x5x10-3 =328 W [1] This is excessive power and usually Flash ADC’s used for maximum of 8-bit conversion. [1] (e) Maximum conversion time when down integration is over 2 14 clock cycles same as up integration. [1] Hence maximum conversion time = 2x2 14 /(40x10 3 )=0.82 seconds . [1] (f) A B Q 1 Q 2 Q 3 Q 4 Z 1 1 1 OPEN OPEN CLOSED CLOSED 1 OPEN CLOSED CLOSED OPEN 1 CLOSED OPEN OPEN CLOSED CLOSED CLOSED OPEN OPEN 1 [3] This is the truth table for a NOR gate. [1] (g) Z=A+AB=A(1+B)=A.1=A [1] (h) (h) [1] A,B,C and F are external signals, D is an internal signal. [1] i) (i) From data sheets, V OH = V CC – 0.2 (for smallest current rating) = 2.5 – 0.2 = 2.3 V. V IH = 1.7 V. [1] for both values. Hence n H = 2.3 V – 1.7 V = 0.6 V . [1] ii) At supply voltage maximum delay = 7.4 ns. Hence delay through two gates is estimated at 2 x 7.4 = 14.8 ns. [1] (j) Dynamic power = CV 2 f [1] Requirement is 50 x 10-12 x 25 x f = 8 x 10-3 in which case f = 6.4 MHz . [1] 2 A B C F D (k) AND requires 3 PMOS and 3 NMOS hence requires 2 “gates”. [1] (l) i) Mealy , because output depends directly on input as well on present state. [1] ii) Present State Next State Output Z X=0 X=1 X=0 X=1 S S S 1 S 1 S S 1 1 [2] iii) One flip-flop because two outputs. [1] (m) If one erases a cell that is already at ‘0’, then the transistor will not work properly because a negative threshold voltage occurs. To avoid this, all cells are pre-programmed to ‘1’ before erasure. [1] (n) i) Isolation capacitors. [1] ii) Intrinsic capacitances of transistor. [1] (o) i) At 300 K: B B I xI x x x r 026 . 10 6 . 1 300 10 38 . 1 19 23 = =-- π At 350 K : B B I xI x x x r 03 ....
View Full Document

{[ snackBarMessage ]}

Page1 / 19

H62ELD Solutions 2008 - H62ELD ELECTRONIC ENGINEERING...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online