Lab06_CacheII_11 - hexadecimal addresses 400 404 408 40C...

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Subject : CC2202 : Computer System Architecture Lab/Tutorial : Session 6 Cache II Subject Lecturer : Steven Chan CC2202-Computer System Architecture Lab 6 Page 1
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1. A computer system has a main memory with capacity consisting of 8MB of data and 8-word blocks. It also has 256 cache lines organized in the direct-mapping manner. a. Calculate the number of bits in each of the TAG, LINE, and WORD fields of the main memory address format. b. Assume associative cache technique is used. Show the appropriate number of bits of TAG, LINE and WORD. 2. A computer has a small data cache of 8 blocks. Each cache block consists of 4 single-byte word. The memory address of the format: A 10 -A 0 The tag field format of the cache: A 10 -A 5. and The line field format of the cache: A 04 -A 02 When a given program is executed, the processor reads data from the following sequence of
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Unformatted text preview: hexadecimal addresses: 400 404 408 40C 4F4 4F0 400 404 418 41C 44C 4F4 (i) Which bit(s) of the address are used to identify a word in a memory block? (ii) Hence, assuming that the cache is initially empty, show the content of the cache at the end of each pass through this loop if a direct mapping cache. Give your answers in the format of Table Given. (iii) What is the hit ratio? 3. A set associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. CC2202-Computer System Architecture Lab 6 Page 2 content block Pass 1 Pass2 Pass3 400 1 2 3 4 5 6 7...
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