Lec11_Pipeline_RISC_show - Lecture 12 CPU Pipelining and...

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CC2202 1 Lecture 12 CPU Pipelining and RISC
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12.3 Instruction Cycle Revision An instruction cycle includes the following subcycles: Fetch Read the next instruction from memory into the CPU Execute Interpret the opcode and perform the indicated operation. Interrupt If interrupts are enabled and an interrupt has occurred, save the current process state and service the interrupt.
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Indirect Cycle Problem: May require memory access to fetch operands Example: Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle
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Instruction Cycle State Diagram
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Data Flow (Instruction Fetch) Depends on CPU design In general: Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1
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Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR
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May take many forms Depends on instruction being executed
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Lec11_Pipeline_RISC_show - Lecture 12 CPU Pipelining and...

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