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Unformatted text preview: ECE 3040 Microelectronic Circuits Exam 3
April 23, 2007 Dr. W. Alan Doolittle Print your name clearly and largely: 50 [unifdaj Instructions: DO NOT TAKE APARTANY PAGES OF THIS EXAM AND SHOWALL WORK ON
THE PROVIDED PAGES. Read all the problems carefully and thoroughly before you
begin working. You are allowed to use 1 new sheet of notes (1 page from and back),
your note sheet from the previous exams as well as a calculator. There are 100 total
points in this exam. Observe the point value of each problem and allocate your time
accordingly. SHOW ALL WORK AND CIRCLE YOUR FINAL ANSWER WITH THE
PROPER UNITS INDICATED. Write legibly. If I cannot read it, it will be considered a
wrong answer. Do all work on the paper provided. Turn in all scratch paper, even if it did not lead to an answer. Report any and all ethics violations to the instructor. Good
luck! Sign your name on ONE of the two following cases: I DID NOT observe any ethical violations during this exam: I observed an ethical violation during this exam: First 30% Multiple Choice and TruefFalse (Select the most correct answer)
1.) (6points total) Identify the bias mode of the following MOS capacitors. (A) Inversi'au (B) AdcamuluIﬁMC) [geekyrich 2.) (4points) For the three capacitors in problem 1, which is true: a They could be used to make a NMOS MOSFET
ey could be used to make a PMOS MOSFET c) The diagrams clearly show the SourceGate bias
d The diagrams clearly show the DrainGate bias
e diagrams clearly show the BodyGate bias 3.) (4points) True enhancement mode NMOS MOSFET was invented after the depletion mode “ I S MOSFET and can conduct current in it’s drainsource circuiteven
with VGS=0 volts. 4.) (4points) In the MOSFET transistor to
the right, what is the voltage across the s D
pinched oﬁ“ region? . ~+ : 
3) VcsVT I b.) VDS k..._._...f““..._m 5L C. VI': \\ ' x 8.) ct enough information given to awn.." solve 5.) ([email protected] False: A well designed current ampliﬁer should have a very low input
resistance. 6.) (9points) Name three improvements that feedback can do to a voltage ampliﬁer 3) Increag Bandwiévhi Tire?, f‘é’ﬁfﬁﬂ‘e) b) Increaﬁe I'hﬂa‘f fee ﬁz'gmnee
c) gearease @Mﬁﬂgt raga; mace wiry/Z, Ailaws {inste gainmi
/ CYEaY€5a Vlﬁr‘i'bbéb/i gnawed 7.) (20points) Sketch and label all break frequencies, the voltage gain in flat regions in a
Bode plot (gain in dB vs Log(frequency)). You may assume that this “Clemson
Designed ” OpA mp is ia‘eair in every way EXCEPT that its open loop gain is an
atrocious 200 V/V. To receive full credit the asymptotes and an estimate of the actual
gain curve should BOTH be sketched on the same plot. Hint: on ma md it he! a! to determine the eedback actor as arto our soiution. Also to make the math easier ieasenotethatﬂa‘m (2“ : Rica. You may also use the following results for the three standard opamp conﬁgurations but these results may or may not be needed for this problem.
’ e .h
4, ‘ 4. Av = VoutNin 2 (R2iR1) Av: Voutitvin = 1+(R2iR1) Av = Vouti'IIVin = 1 ..... m,_____ Extra work can be done here, but clearly indicate with problem you are solving. 71m Pulling all the concepts together for a useful purpose: 8.) [SOgain“) Given the following circuit, (a) Identify the conﬁguration of BOTH of the two stages (common 1. (b) What is the AC voltage gain, Vomfvtn? You may
assume all capacitors have inﬁnite capacitance. You may assume all inductors have inﬁnite
inductance. Additionally consider the circuit to be operated at low frequencies where you can
neglect all small signal capacitances. Grading will be based as such: part a=5 points, part b=18 points for DC solution (gate, source
and drain voltages along with drain current), 9 points for the conversion to the small signal
model and 18 points for small signal analysis. IDC SUUA 0 —9V Vin R1
J7 100K
t C 0 Use the following parameters (note that VT and 7t vary with transistor type): Wm.» m R2 _
800K R3 M1 0 t 6 R4
4
100k _ 900K V°Ut
5
1
170‘ 9. 10K U...“ ..._ _. t.. .....__._....... “I‘m<uﬁ up.
av... Lu.. _=_... ..... ‘__...— h a For NMOS Depletion Transistors:
Kn’=20 uh/v2 VT= 4.0V 7L=0.0 V'1 Length (L): 10 um Width (W)= 10 um ‘__um” m» in..." _q_ _’
""'—'*w“‘" “Mm 1““me m 1 For NMOS Enhancement Transistors:
K,'=30 uA/V2 VT= +0. 75v 7t=0.1V" Length _(L)_=1o urn Width (W) 10 um ,_..........__............ _.,.._....... .d ”m... .H. 4.. _...,.. ...._.4....... .._..n......u~.. For PMOS Depletion Transistors:
Kp’=40 uA/V2 VT: +3.0V SL=0.0 V'l Length (L)=10 um Width (W)=10 um For PMOS Enhancement Transistors:
K,’=50 uANz VT= I.75V h=0.1 V'1 Length (L)=10 um Width (W)=10 um Part a) 51‘015‘3 1 Common Source
éiage Q Camm0" [Zrm}, Extra work can be done' here, but clearly indicate with problem you are solving. 0&3 “W
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 Spring '11
 Doolittle

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