Lecture33-MOS Logic Gate Design

Lecture33-MOS Logic Gate Design - ecture 33 Lecture 33...

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Unformatted text preview: ecture 33 Lecture 33 Digital Logic Gates Reading: Jaeger 6.6-6.9, 7.1-7.5 and Notes ECE 3040 - Dr. Alan Doolittle Georgia Tech Resistive Load Inverter Pull Up Resistor provides current to Charge p the Load Capacitor C Load Capacitor, C L , represents the t l it f ll t th t up the Load Capacitor, C L total capacitance of all gates that would be connected to the output (Input capacitance's of the MOSFETS) C L Switching transistor will Pull down the output voltage by discharging the Load Capacitor, C l when the transistor is ECE 3040 - Dr. Alan Doolittle Georgia Tech conducting. Note: V BS =0 Resistive Load Inverter Inverter State: Input is Low Output is High C L R i V v v D S D DD DS o For v i =v GS =V OL <V T OH DD o D V V v i V OL <V T is our first design criteria! ECE 3040 - Dr. Alan Doolittle Georgia Tech For a nominal V T = 1, we would typically make V OL ~0.25V to insure adequate noise margin. Resistive Load Inverter Inverter State: Input is High Output is Low C L D S i V v v D DD DS o For v i =v GS =V OH =V DD from previous page, v o =V OL ! region linear the in be must we v V v Since DS DD GS ECE 3040 - Dr. Alan Doolittle Georgia Tech Resistive Load Inverter The MOSFET switches between the two operating points, v GS <V T (cutoff) and v GS =V DD (Linear) along a Resistive (linear IV characteristic) Load Line passing through the saturation region during the transition. v GS =V DD (Linear) ECE 3040 - Dr. Alan Doolittle Georgia Tech v GS <V T (cutoff) Resistive Load Inverter xample: If we wanted the gate to dissipate 0 25 mW using a Example: If we wanted the gate to dissipate 0.25 mW using a V TN =1V and K n =25e-6 A/V 2 , and having a V OL =0.25V, what W/L ratio would be needed? What load resistance is required? Since, i e xi V Power S DS DD 5 3 25 . v v V v W K i A i S S N S S DS S 5 . 50 ' L W e e L DS DS TN GS n DS 25 . 125 . 1 5 6 25 6 50 L W 1 06 . 2 ECE 3040 - Dr. Alan Doolittle Georgia Tech K e i V V R DS OL DD 95 6 50 25 . 5 Resistive Load Inverter So far we have (V OH =5V) and (V OL =0.25V<<V T ). We now need V IL and V IH . ECE 3040 - Dr. Alan Doolittle Georgia Tech Resistive Load Inverter Calculating V Since when v i =V IL , v GS is small but clearly greater an V ransistor is conducting as observed from the IL than V T (transistor is conducting as observed from the output voltage being reduced) and since v DS is large, we will assume saturation. nd 2 dv R V v K V v R i V v and V V K i o TN i n DD o DS DD o TN GS n DS 5 ....
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This note was uploaded on 08/23/2011 for the course ECE 3040 taught by Professor Doolittle during the Spring '11 term at University of Florida.

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Lecture33-MOS Logic Gate Design - ecture 33 Lecture 33...

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