11-Narasimhan_3-D Semiconductors

11-Narasimhan_3-D Semiconductors - 3-D Semiconductors...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 3-D Semiconductors Sriram Narasimhan ECE 3080 Fall 2004 Background Moore’s law: the number of transistors on an integrated circuit will double every 18 months For 90nm gates, the chip can have up to 7km of interconnects per square centimeter The long­term solution? Build vertically! 3­D IC’s are commonly called Monolithic High Density Multifunctional Integration Advantages/Applications Essentially stacks multiple dies via global interconnections through them (not the same as 3­D packaging) • • • Allows for shorter wires (~1um), reducing delays Transistors can be built smaller Reduces power consumption Each “layer” can be optimized for a different function • Example: photo detection processor Pixel arrays uses GaNi, InP; DSP uses Si Two Methods Flip­chip­on­chip • • • Bond pads carry I/O connections Reduces global interconnect lengths 30% Only allows up to 2 dies to be connected Direct vertical connection • Annular vias (holes) allow for multiple chips to be held together • Blind via, Via­last processes Via-last Other Considerations Via­first • Lower cost, vias can be made while transistors are being fabricated Via­last • More precise and less defects between substrates (due to seamless covalent bonding), but more costly Via-last: Four Steps to Success Wafer alignment Low­k dielectric glue between layers Thinning & planarization of top layer Inter­wafer Cu interconnections Thinning & Planarization More connections are made possible Consistency of dimensions is preserved Vias must have short lengths and a minimum aspect ratio Process: • First step requires polishing using Chemical­ Mechanical Planarization (CMP) to ~50um • Second step uses chemical, mechanical, reactive ion etching to ~10um Effects of HDMI on RAM More cache can be placed on a single die 20­30% better performance Reduction of the size of board area Shorter interconnects reduce power consumption Questions? ...
View Full Document

This note was uploaded on 08/23/2011 for the course ECE 3080 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

Ask a homework question - tutors are online