ECE6450L15 Process integration

ECE6450L15 Process integration - Lecture 15 Process...

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ECE 6450 - Dr. Alan Doolittle Georgia Tech Lecture 15 Process Integrations Reading: Selections from Chapters 15-18
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ECE 6450 - Dr. Alan Doolittle Georgia Tech Analog Technology: Bipolar Junction Transistors Consider a lateral npn transistor (makes up a significant percentage of analog devices used) 1.) Diffuse a n-type (20-50 ohms/sq) “buried layer” into a p- type (~1e16 Boron doped) wafer. 2.) Use CVD to grow a high quality, single crystal epitaxial layer. If a BVCEO=36 V is desired, a reasonable margin of error is a C-B depletion width that can withstand 90V. This requires an epitaxial width of: 6 um @ 1e15 for depletion width in collect. +8 um due to buried layer diffusion +3 um required for the base 17 um thick CVD layer 3.) Isolation diffusion or Trenches A very high temperature, long time p-type (~20-40 ohms/sq.) diffusion must be formed to “isolate” one device from another. Alternatively a trench can be etched, p-type implanted, oxidized, filled with poly-Si and re-oxidized (will describe this later in MOS discussion).
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ECE 6450 - Dr. Alan Doolittle Georgia Tech Analog Technology: Bipolar Junction Transistors 4.) The p-type (100-300 ohms/sq) base is diffused ~1-3 um deep. 5.) The n-type (2-10 ohms/sq.) emitter and a low resistance collector contact pad is simultaneously diffused ~0.5 to 2.5 um. The 6.)
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ECE6450L15 Process integration - Lecture 15 Process...

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