lecture_10 - ECE 190 Lecture 10 February 17, 2011 LC-3 ISA...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 190 Lecture 10 February 17, 2011 1 V. Kindratenko LC-3 ISA - II Lecture Topics LC-3 data movement instructions LC-3 control instructions Example Lecture materials Textbook § 5.3 - 5.6 Textbook Appendix A.3 Homework HW3 due Wednesday February 23 at 5pm in the ECE 190 drop-off box Machine problem MP2 due March 2, 2011 at 5pm submitted electronically. Announcements
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ECE 190 Lecture 10 February 17, 2011 2 V. Kindratenko LC-3 data movement instructions Overview Load: move data from memory to register o LD, LDI, LDR o LEA – immediate mode load instruction Store: o ST, STR, STI Load/store instruction format opcode destination or source register address generation bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 ways to interpret address generation bits (4 addressing modes) o PC-relevant mode (LD and ST instructions) o Indirect mode (LDI and STI instructions) o Base + offset mode (LDR and STR instructions) o Immediate mode (LEA instruction) Load instruction using base + offset addressing mode (LDR) Operation: the content of memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign-extended last 6 bits of the instruction (offset6) is loaded into the destination register (DR) o DR ← mem[BaseR+SEXT(offset6)] o setcc Encoding: 0 opcode 1 1 0 destination register offset6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LDR base address register Datapath relevant to the execution of this instruction: o Example: 0110 001 010 011101; LDR R1, R2, offset
Background image of page 2
ECE 190 Lecture 10 February 17, 2011 3 V. Kindratenko xABCD x2345 R0 R1 R2 R3 R4 R5 R6 R7 ADD 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 IR 6 DR 3 SEXT IR[5:0] 16 xABCD MDR MAR 16 16 x1D x2362 x2362 BaseR 3 1 0 0 N Z P MAR ← R2 + SEXT(IR[5:0]) MDR ← mem[MAR] R1 ← MDR offset6 field is 6-bit wide, thus the offset can be from -32 to +31 Store instruction using base + offset addressing mode (STR) Operation: value stored in the source register (SR) is transferred to the memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign- extended last 6 bits of the instruction (offset6) o mem[BaseR+SEXT(offset9)] ← SR Encoding: 0 opcode 1 1 1 source register offset6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STR base address register Datapath relevant to the execution of this instruction: o Example: 0111 001 010 011101; STR R1, R2, offset
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ECE 190 Lecture 10 February 17, 2011 4 V. Kindratenko xFEDC x2345 R0 R1 R2 R3 R4 R5 R6 R7 ADD 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 IR 6 SR 3 SEXT IR[5:0] 16 xFEDC MDR MAR 16 16 x1D x2362 x2362 BaseR 3 MAR ← R2 + SEXT(IR[5:0]) MDR ← R1 mem[MAR] ← MDR Load instruction using PC relative addressing mode (LD) Operation: the content of memory at the address computed as the sum of the address stored in PC register and the sign-extended last 9 bits of the instruction (PCoffset9) is loaded into the
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 08/24/2011 for the course ECE 190 taught by Professor Hutchinson during the Spring '08 term at University of Illinois, Urbana Champaign.

Page1 / 12

lecture_10 - ECE 190 Lecture 10 February 17, 2011 LC-3 ISA...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online