24C256 - Features Low Voltage and Standard Voltage...

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Features Low Voltage and Standard Voltage Operation – 5.0 (V CC = 4.5V to 5.5V) – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 3.6V) Internally Organized 16,384 x 8 and 32,768 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 64-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (5 ms typical) High Reliability – Endurance: 100,000 Write Cycles – Data Retention: 40 Years – ESD Protection: > 4000V Automotive Grade and Extended Temperature Devices Available 8-Pin JEDEC PDIP, 8-Pin JEDEC and EIAJ SOIC, 14-Pin TSSOP, and 8-Pin Leadless Array Packages Description The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica- tions where low power and low voltage operation are essential. The devices are avail- able in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin TSSOP, and 8-pin LAP packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions. Rev. 0670C–08/98 2-Wire Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) AT24C128 AT24C256 Pin Configurations Pin Name Function A 0 to A 1 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect 8-Pin PDIP 1 2 3 4 8 7 6 5 A0 A1 NC GND VCC WP SCL SDA 8-Pin SOIC 1 2 3 4 8 7 6 5 A0 A1 NC GND VCC WP SCL SDA 8-Pin Leadless Array Bottom View 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 NC GND 14-Pin TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A0 A1 NC NC NC NC GND VCC WP NC NC NC SCL SDA
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AT24C128/256 2 Absolute Maximum Ratings* Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A 1 and A 0 are zero. WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC , all write operations to the memory are inhib- ited. If left unconnected, WP is internally pulled down to GND. Switching WP to V CC prior to a write operation cre- ates a software write protect function.
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This note was uploaded on 08/24/2011 for the course ECE 231 taught by Professor Damodar during the Spring '10 term at IIT Kanpur.

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24C256 - Features Low Voltage and Standard Voltage...

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