fm - A VHDL Primer Jayaram Bhasker American Telephone and...

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A VHDL Primer Jayaram Bhasker American Telephone and Telegraph Company Bell Laboratories Division P T R Prentice Hall Englewood Cliffs, New Jersey 07632
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Dedicated to my parents, Nagamma and Appiah Jayaram ii
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Contents Preface vi CHAPTER 1. Introduction 1 1.1. What is VHDL? 1 1.2. History 1 1.3. Capabilities 1 1.4. Hardware Abstraction 2 CHAPTER 2. A Tutorial 4 2.1. Basic Terminology 4 2.2. Entity Declaration 5 2.3. Architecture Body 6 2.3.1. Structural Style of Modeling 6 2.3.2. Dataflow Style of Modeling 7 2.3.3. Behavioral Style of Modeling 8 2.3.4. Mixed Style of Modeling 9 2.4. Configuration Declaration 10 2.5. Package Declaration 11 2.6. Package Body 12 2.7. Model Analysis 12 2.8. Simulation 13 CHAPTER 3. Basic Language Elements 14 3.1. Identifiers 14 3.2. Data Objects 14 3.3. Data Types 16 3.3.1. Subtypes 16 3.3.2. Scalar Types 16 3.3.3. Composite Types 19 3.3.4. Access Types 22 3.3.5. Incomplete Types 2 3 3.3.6. File Types 2 4 3.4. Operators 25 3.4.1. Logical Operators 26 3.4.2. Relational Operators 26 3.4.3. Adding 0perators 26 3.4.4. Multiplying 0perators 26 3.4.5. Miscellaneous Operators 27 CHAPTER 4. Behavioral Modeling 28 4.1. Entity Declaration 28 4.2. Architecture Body 28 4.3. Process Statement 29 4.4. Variable Assignment Statement 30 4.5. Signal Assignment Statement 30 4.6. Wait Statement 31 4.7. If Statement 32 4.8. Case Statement 33 4.9. Null Statement 34 4.10. Loop Statement 34 iii
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4.11. Exit Statement 35 4.12. Next Statement 36 4.13. Assertion Statement 37 4.14. More on Signal Assignment Statement 38 4.14. 1 . Inertial Delay Model 38 4.14.2. Transport Delay Model 38 4.14.3. Creating Signal Waveforms 39 4.14.4. Signal Drivers 39 4.15. Other Sequential Statements 42 4.16. Multiple Processes 42 CHAPTER 5. Dataflow Modeling 44 5.1. Concurrent Signal Assignment Statement 44 5.2. Concurrent versus Sequential Signal Assignment 45 5.3. Delta Delay Revisited 46 5.4. Multiple Drivers 47 5.5. Conditional Signal Assignment Statement 49 5.6. Selected Signal Assignment Statement 50 5.7. Block Statement 5 0 5.8. Concurrent Assertion Statement 53 CHAPTER 6. Structural Modeling 54 6.1. An Example 54 6.2. Component Declaration 54 6.3. Component Instantiation 55 6.4. Other Examples 57 6.5. Resolving Signal Values 59 CHAPTER 7. Generics and Configurations 61 7.1. Generics 6 1 7.2. Why Configurations? 63 7.3. Configuration Specification 63 7.4. Configuration Declaration 67 7.5. Default Rules 69 CHAPTER 8. Subprograms and Overloading 71 8.1. Subprograms 7 1 8.1.1. Functions 7 1 8.1.2. Procedures 7 2 8.1.3. Declarations 74 8.2. Subprogram Overloading 74 8.3. Operator Overloading 76 CHAPTER 9. Packages and Libraries 78 9.1. Package Declaration 78 9.2. Package Body 79 9.3. Design Libraries 7 9 9.4. Design File 8 0 9.5. Order of Analysis 80 9.6. Implicit Visibility 81 9.7. Explicit Visibility 81 9.7.1. Library Clause 82 9.7.2. Use Clause 82 iv
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CHAPTER 10. Advanced Features 84 10.1. Entity Statements
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fm - A VHDL Primer Jayaram Bhasker American Telephone and...

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