EE201L_RTL_coding_style_verilog

EE201L_RTL_coding_style_verilog -...

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EE201L_RTL_coding_style_verilog.fm 2/24/09 1 C Copyright 2009 Gandhi Puvvada RTL Coding style and when we need to deviate from such a style In FPGA/ASIC design, it is recommended that you adopt a pure synchronous design methodology as much as possible. Synthesizers can interpret (and map) such designs successfully. Synchronous design In a good synchronous design, you perform -- register transfers only on significant clock edges -- avoid latches -- avoid asynchronous loading of registers/counters using direct set/direct clear -- avoid asynchronous setting/resetting of flip-flops acting as status/flags -- avoid level sensitive (asynchronous) RAM write operations In a synchronous design, you compute the value (to be deposited in a destination register) ahead of the arrival of the clock edge (at least setup time before the clock edge) and deposit the value at the clock edge. The computation logic is a combinational logic such as an incrementer in the case of a counter. Two major coding choices Two coding styles are described below. The first choice amounts to performing low level design by hand. Most engineers tend to use this style initially because they have been performing hand- designs / schematic-based designs and they are perhaps using HDL for the first time. Very soon, they realize the power of inference by the synthesis tools and start coding using the second style called RTL coding style. Experienced designers will occasionally use the first coding style to cater for special cases requiring deliberate deviation from the synchronous style of designing (or to overcome the limitations of the synthesis tools). Coding choice #1 (low-level coding, trying to translate the schematic design into HDL) In this choice of coding, separate combinational always procedural blocks/continuous assign- ments are used for all combinational logic. Clocked always procedural blocks are used just to update registers with the values computed by the combinational always procedural blocks. For example coding NSL (Next State Logic) by hand in a combinational always procedural block and having a clocked always procedural block just to update the Current_State with the value of the Next_State (as computed by the combinational always procedural block) comes under this style of coding. In a datapath, if a register X is loaded with Xin in the initial state, and with (X - Y) in a later com- putational state, one can visualize a subtractor to calculate (X - Y) and a multiplexer to select between Xin and (X - Y) and code them as combinational blocks. One also needs to think of the control signals such as X_Mux_Select and X_Load and write a combinational block OFL (Out- put Function Logic) to generate those signals.
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EE201L_RTL_coding_style_verilog.fm 2/24/09 2 C Copyright 2009 Gandhi Puvvada
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This note was uploaded on 08/25/2011 for the course EE- 201 taught by Professor Gandhipuvvada during the Spring '11 term at USC.

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EE201L_RTL_coding_style_verilog -...

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