Basic_Pipelining

Basic_Pipelining - CSCE 430/830 Computer Architecture Basic...

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CSCE 430/830 Computer Architecture Basic Pipelining & Performance Adopted from Professor David Patterson Electrical Engineering and Computer Sciences University of California, Berkeley
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 2 Outline MIPS – An ISA for Pipelining 5 stage pipelining Structural and Data Hazards Forwarding Branch Schemes Exceptions and Interrupts Conclusion
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 3 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement no indirection Simple branch conditions Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 4 Example: MIPS (- MIPS) Op 31 26 0 15 16 20 21 25 Rs1 Rd immediate 0 0 Rs2 target Opx Register-Register 5 6 10 11 Register-Immediate 0 Rs2/Opx Branch Jump / Call
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 5 Datapath vs Control Datapath: Storage, FU, interconnect sufficient to perform the desired functions Inputs are Control Points Outputs are signals Controller: State machine to orchestrate operation on the data path Based on desired function and signals Datapath Controller Control Points signals
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 6 Approaching an ISA Instruction Set Architecture Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing Meaning of each instruction is described by RTL (Register Transfer Language) on architected registers and memory Given technology constraints assemble adequate datapath Architected storage mapped to actual storage Function units to do all the required operations Possible additional storage (eg. MAR, MBR, …) Interconnect to move information among regs and FUs Map each instruction to sequence of RTLs Collate sequences into symbolic controller state transition diagram (STD) Lower symbolic STD to control points Implement controller
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 7 5 Steps of MIPS Datapath Figure A.2, Page A-8 Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc L M D ALU MUX Reg File Data Sign Extend 4 Adder Zero? Next SEQ PC Address Next PC WB Data Inst RD RS1 RS2 Imm IR <= mem[PC]; PC <= PC + 4 Reg[IR rd ] <= Reg[IR rs1 ] op IRop Reg[IR rs2 ]
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08/28/11 CSCE 430/830, Basic Pipelining & Performance 8 5 Steps of MIPS Datapath Figure A.3, Page A-9 Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc ALU Reg File MUX Data Sign Extend Zero? IF/ID ID/EX MEM/WB EX/MEM 4 Adder Next SEQ PC RD WB Data Next PC Address RS1 RS2 Imm IR <= mem[PC]; PC <= PC + 4 A <= Reg[IR rs1 ]; B <= Reg[IR rs2 ] rslt <= A op IRop B Reg[IR rd ] <= WB WB <= result
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CSCE 430/830, Basic Pipelining & Performance 9 Inst. Set Processor Controller IR <= mem[PC]; PC <= PC + 4 A <= Reg[IR rs1 ]; B <= Reg[IR rs2 ] r <= A op IRop B Reg[IR rd ] <= WB
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Basic_Pipelining - CSCE 430/830 Computer Architecture Basic...

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