vlsi - VLSI Technology VLSI Scaling s Moore’s Law s 3D...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: VLSI Technology VLSI Scaling s Moore’s Law s 3D VLSI 3D VLSI s The beginning The Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, home appliances and of course, computers. Transistors are the main components of microprocessors. microprocessors. At their most basic level, transistors may seem At simple. But their development actually required many years of painstaking research. Before transistors, computers relied on slow, inefficient vacuum tubes and mechanical switches to process information. In 1958, engineers managed to put two information. transistors onto a Silicon crystal and create the first Silicon integrated circuit, which subsequently led to the first integrated led performance i mproves as size is decreased: MOSFET Transistor Size Scaling Transistor shorter switching time, l ower power consumption. 2 orders of magnitude reduction in transistor size in 30 years. Significant Breakthroughs Significant Transistor size: Intel’s research labs have recently shown the world’s smallest transistor, with a gate length of 15nm. We continue to build smaller and smaller transistors that are faster and faster. We've reduced the size from 70 nanometer to 30 nanometer to 20 nanometer, and now to 15 nanometer gates. Manufacturing process: A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1,000 of these "wires" placed side-by-side to equal the width of a human hair. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds. Wafer size: Wafers, which are round polished disks made of silicon, provide the base on which chips are manufactured. Use a bigger wafer and you can reduce manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size, up from the previous wafer size of 200mm (about 8 inches). Major Design Challenges Major s Microscopic issues – ultra-high speeds – power dissipation and power supply rail drop supply – growing importance of growing interconnect interconnect – noise, crosstalk – reliability, reliability, manufacturability manufacturability – clock distribution s Macroscopic issues – time-to-market – design complexity design (millions of gates) (millions – high levels of high abstractions abstractions – design for test – reuse and IP, portability – systems on a chip (SoC) – tool interoperability Year Tech. Complexity Frequency Staff Size Staff Costs 1997 0.35 13 M Tr. 400 MHz 210 $90 M 1998 0.25 20 M Tr. 500 MHz 270 $120 M 1999 0.18 32 M Tr. 600 MHz 360 $160 M 2002 0.13 130 M Tr. 800 MHz 800 $360 M Integrated Circuits Integrated s Digital logic is implemented using transistors in integrated circuits Digital transistors integrated containing many gates. containing – – – – s small-scale integrated circuits (SSI) contain 10 gates or less medium-scale integrated circuits (MSI) contain 10-100 gates large-scale integrated circuits (LSI) contain up to 104 gates very large-scale integrated circuits (VLSI) contain >104 gates Improvements in manufacturing lead to ever smaller transistors Improvements allowing more per chip. allowing – >107 gates/chip now possible; doubles every 18 months or so s Variety of logic families – – – – TTL - transistor-transistor logic CMOS - complementary metal-oxide semiconductor ECL - emitter-coupled logic GaAs - gallium arsenide What are shown on previous diagrams cover only the so called front‑end processing ‑ fabrication steps that go towards forming the devices and inter‑connections between these devices to produce the functioning IC's. The end result are wafers each containing a regular array of the same IC chip or die. The wafer then has to be tested and the chips diced up and the good chips mounted and wire‑bonded in different types of IC package and tested again before being shipped out. before From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall Moore’s Law Moore’s s s Gordon E. Moore - Chairman Emeritus of Intel Corporation 1965 - observed trends in industry - # of transistors on ICs vs. release dates: 1965 – Noticed number of transistors doubling with release of each new Noticed IC generation IC – release dates (separate generations) were all 18-24 months apart s Moore’s Law: – The number of transistors on an integrated circuit will double The every 18 months every s s s s The level of integration of silicon technology as measured in terms of The number of devices per IC IC This comes about in two ways – size reduction of the individual devices and This increase in the chip or dice size increase As an indication of size reduction, it is interesting to note that feature size As was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10-6 m or 10-4 cm) whereas Semiconductor industry has followed this prediction with surprising Semiconductor accuracy accuracy Moore’s Law • • In 1965, Gordon Moore predicted that the number of transistors that can be In integrated on a die would double every 18 to 14 months integrated • i.e., grow exponentially with time Amazing visionary – million transistor/chip barrier was crossed in the 1980’s. – 2300 transistors, 1 MHz clock (Intel 4004) - 1971 – 42 Million, 2 GHz clock (Intel P4) - 2001 – 140 Million transistor (HP PA-8500) Source: Intel web page (www.intel.com) Moore’s Law Moore’s s From Intel’s 4040 (2300 transistors) to Pentium II From (7,500,000 transistors) and beyond (7,500,000 Relative sizes of ICs in graph Ever since the invention of integrated circuit, the smallest feature size has been reducing every year. Currently (2002) the smallest feature size is about 0.13 micron. At the same time the number transistors per chip is increasing due to feature size reduction and increase in chip area. Classic example is the case of memory chips: Gordon Moore of Intel in early 1970s found that: “density” (bits per chip) growing at the rate of four times in 3 to 4 years - often referred to as Moore’s Law. In subsequent years, the pace slowed down a bit, data density has doubled approximately every 18 months – current definition of Moore’s Law. approximately Limits of Moore’s Law? Limits s Growth expected until 30 nm gate length (currently: 180 nm) – size halved every 18 mos. - reached in size 2001 + 1.5 log2((180/30)2) = 2009 s – what then? Paradigm shift needed in fabrication process Technological Background of the Moore’s Law Law s s s To accommodate this change, the size of the silicon To wafers on which the integrated circuits are fabricated have also increased by a very significant factor – from the 2 and 3 in diameter wafers to the 8 in (200 mm) and the 12 in (300 mm) diameter wafers 12 The latest catch phrase in semiconductor technology (as The well as in other material science) is nanotechnology – usually referring to GaAs devices based on quantum mechanical phenomena mechanical These devices have feature size (such as film thickness, These 9 line width etc) measured in nanometres or 10--9 metres line metres Recurring Costs Recurring packaging cost of die + cost of die test + cost of packaging variable cost = variable ------------------------------------------------------------------------------------------------------------------------------final test yield final cost of wafer cost cost of die = ----------------------------------dies per wafer × die yield dies die π × (wafer diameter/2)2 π × wafer diameter (wafer wafer dies per wafer = ---------------------------------- − ----------------------------------------------------die area √ 2 × die area die yield die = (1 + (defects per unit area × die area)/α)-α Yield Example Yield Example q q 252 dies/wafer (remember, wafers round & dies square) q die yield of 16% q wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, α = 3 (measure of manufacturing process complexity) 252 x 16% = only 40 dies/wafer die yield ! Die cost is strong function of die area proportional to the third or fourth power of the die area Intel 4004 Microprocessor Intel Intel Pentium (IV) Microprocessor Intel Die Size Growth Die Die size grows by 14% to satisfy Moore’s Law Die size (mm) 100 10 8080 8008 4004 8086 8085 286 386 P6 486 Pentium ® proc ~7% growth per year ~2X growth in 10 years 1 1970 1980 1990 Year Courtesy, Intel 2000 2010 Clock Frequency Clock Lead microprocessors frequency doubles every 2 years 10000 2X every 2 years Frequency (Mhz) 1000 P6 100 486 10 8085 1 0.1 1970 8086 286 Pentium ® proc 386 8080 8008 4004 1980 1990 Year Courtesy, Intel 2000 2010 Examples of Cost Metrics (1994) Examples Chip Metal Metal layers layers Line Line width width Wafer Defects/ Area Wafer Area cost cm2 (mm2) cost (mm Dies/ Yield wafer Die Die cost cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486DX2 3 0.80 $1200 1.0 81 181 54% $12 PowerPC PowerPC 601 601 4 0.80 $1700 1.3 121 115 28% $53 HP PA HP 7100 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC DEC Alpha Alpha 3 0.70 $1500 1.2 234 53 19% $149 Super Super SPARC SPARC 3 0.70 $1700 1.6 256 48 13% $272 Pentium 3 0.80 $1500 1.5 296 40 9% $417 VLSI VLSI s Very Large Scale Integration – design/manufacturing of extremely small, complex circuitry design/manufacturing using modified semiconductor material using – integrated circuit (IC) may contain millions of transistors, integrated each a few µ m in size – applications wide ranging: most electronic logic devices Origins of VLSI Origins s s s s s Much development motivated by WWII need for improved Much electronics, especially for radar electronics, 1940 - Russell Ohl (Bell Laboratories) - first pn junction 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) 1948 first transistor first – 1956 Nobel Physics Prize Late 1950s - purification of Si advances to acceptable Late levels for use in electronics levels 1958 - Seymour Cray (Control Data Corporation) - first 1958 transistorized computer - CDC 1604 transistorized Origins of VLSI (Cont.) Origins s s s s s 1959 - Jack St. Claire Kilby (Texas Instruments) - first 1959 integrated circuit - 10 components on 9 mm2 integrated 1959 - Robert Norton Noyce (founder, Fairchild 1959 Semiconductor) - improved integrated circuit Semiconductor) 1968 - Noyce, Gordon E. Moore found Intel 1971 - Ted Hoff (Intel) - first microprocessor (4004) 1971 2300 transistors on 9 mm2 2300 Since then - continued improvement in technology has Since allowed for increased performance as predicted by Moore’s Law Moore’s Three Dimensional VLSI Three s s The fabrication of a single integrated circuit whose functional The parts (transistors, etc) extend in three dimensions parts The vertical orientation of several bare integrated circuits in a The single package single Advantages of 3D VLSI Advantages s Speed - the time required for a signal to travel between the functional circuit Speed blocks in a system (delay) reduced. blocks – Delay depends on resistance/capacitance of interconnections – resistance proportional to interconnection length Advantages of 3D VLSI Advantages s s Noise - unwanted disturbances on a useful signal – reflection noise (varying impedance along interconnect) – crosstalk noise (interference between interconnects) – electromagnetic interference (EMI) (caused by current in pins) 3D chips – fewer, shorter interconnects – fewer pins Advantages of 3D VLSI Advantages s Power consumption – power used charging an interconnect capacitance » P = fCV2 – power dissipated through resistive material » P = V2/R – capacitance/resistance proportional to length – reduced interconnect lengths will reduce power Advantages of 3D VLSI Advantages s Interconnect capacity (connectivity) – more connections between chips – increased functionality, ease of design Advantages of 3D VLSI Advantages s Printed circuit board size/weight – planar size of PCB reduced with negligible IC height increase – weight reduction due to more circuitry per package/smaller PCBs – estimated 40-50 times reduction in size/weight 3D VLSI - Challenges and Solutions 3D s s Challenge: Thermal management – smaller packages – increased circuit density increased – increased power density Solutions: – circuit layout (design stage) » high power sections uniformly distributed – advancement in cooling techniques (heat pipes) Influential Participants - Industry Influential s s s Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors, others... – high density memories AT&T – high density “multiprocessor” Many other applications/participants Three Dimensional VLSI Three s s s Moore’s Law approaching physical limit Increased performance expected by market Paradigm shift needed - 3D VLSI – many advantages over 2D VLSI – economic limitations of fabrication overhaul will be overcome by economic market demand market s Three Dimensional VLSI may be the savior of Moore’s Law ...
View Full Document

This note was uploaded on 08/29/2011 for the course ECE 265 taught by Professor Kosbar during the Fall '09 term at Missouri S&T.

Ask a homework question - tutors are online