10-interrupts - 68HC11 = processor family 68HC11 A8 memory...

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68HC11 = processor family 68HC11 A8 memory map $0000 $00FF $1000 $103F $B600 $B7FF $E000 $FFFF RAM I/O registers EEPROM ROM
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68HC11 Hardware Resources
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68HC11 2 modes single-chip Address + data busses not accessible, but I/O ports are expanded Address + data busses accessible, but some I/O ports (B and C) not Mode selection on power-on (MDDA, MDDB inputs)
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Programmable In/Out Ports A, C, D Have additional register: Data Direction Register (DDRA at $1026, DDRC at $1007, DDRD at $1009) bit i = 0 → corresponding port pin i input 1 → corresponding port pin i output After processor reset: DDR x = 0 → all inputs
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Programmable In/Out Port Example Port C C 0 C 7 PORTC EQU $1003 DDRC EQU $1007 ORG $C000
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I/O - Processor synchronization ? How does I/O signal processor that it has data? processor core I/O ready (STRA) Input port latch I/O data 8 bits PORTCL $1005
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I/O - Processor synchronization PIOC register (Parallel I/O control register) at $1002 STAF 0 1 7 EGA EGA = 0 → STRA 1 → STRA When correct edge on STRA: 1. input value will be clocked into PORTCL latch 2. STAF flag will be set To reset STAF flag (done in program): LDAA PIOC LDAA PORTCL
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I/O - Processor synchronization Polling (using STRA and STAF flag) Interrupt Polling init Did I/O device Set STAF? No Yes clear STAF flag get data process data
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Polling Example Keyboard and display connected to processor Program: if key pressed, read data in and send it to display 4-bit data (both keyboard and display) 1-bit that signals through a 0 that a key is pressed Data only available while key pressed processor keyboard data key pressed Port C (bits 0 to 3) STRA 4 bits display 4 bits Port C (bits 4 to 7) when key pressed
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Polling Example PIOC EQU $1002 PORTC EQU $1003 PORTCL EQU $1005 DDRC EQU $1007 ORG $C000 MAIN
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10-interrupts - 68HC11 = processor family 68HC11 A8 memory...

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