4-instruction cycles

4-instruction cycles - Instruction Cycles Tathagata...

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Tathagata Bhattacharjee Instruction Cycles Tathagata Bhattacharjee
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Tathagata Bhattacharjee Single-Cycle CPU • Clock cycle is determined by the longest possible path in the machine – loads are the worst • Performance, utilization, and efficiency are not going to be good, because most instructions don’t need such a long clock cycle • A variable-speed clock could be used to solve this problem, but hinders parallelism – Pipelining overlaps instruction executions
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Tathagata Bhattacharjee Multicycle Implementation • Break instructions into steps, where each step requires one clock cycle • We want to reuse functional units within an instruction instead of just across instructions – Reduces hardware • Use single memory for instructions and data • Single ALU instead of one ALU and two adders • Add registers to functional units to hold intermediate results (state data) for future cycles – Use within instruction executions • Register file and memory hold state data to be used across instruction executions – These are programmer-visible • We will need a FSM to control CPU
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This note was uploaded on 07/15/2011 for the course ECO 2023 taught by Professor Mr.raza during the Summer '10 term at FAU.

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4-instruction cycles - Instruction Cycles Tathagata...

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