CPUMod - Single-cycle CPU: Implementation of Loop...

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Single-cycle CPU: Implementation of Loop Instruction Take the Single Cycle datapath posted on the web, and modify it so that it can also execute the instruction loop r1, r2, offset This is a branch instruction that increments register r1, and compares it to a loop bound of r2. If these two values are not equal then the PC is set to PC + offset. The instruction uses the Immediate MIPS instruction format. This instruction has the same effect as sequentially executing the following two instructions on the MIPS architecture: addi r1, r1, 1 bne r1, r2, offset For this question do NOT modify the instruction memory, data memory, or the register file. You can only modify/add control lines, MUXs, ALUs, and data path lines. To answer this question (1) give the above sequence of instructions using the rs, rt, rd, and immediate fields from the immediate format, (2) draw the parts of the datapath that have changed, and (3) give the state for the control for this instruction in the modified datapath. For the state show the values for all the control lines and any MUX in the original Single
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This note was uploaded on 07/15/2011 for the course ECO 2023 taught by Professor Mr.raza during the Summer '10 term at FAU.

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CPUMod - Single-cycle CPU: Implementation of Loop...

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