L9 - Multiple Clock Cycle CPU or Breaking Up Is Hard To Do...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
CSE 141 Allan Snavely Multiple Clock Cycle CPU or Breaking Up Is Hard To Do CSE 141 Allan Snavely Why a Multiple Clock Cycle CPU? the problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine the solution => break up execution into smaller tasks, each task taking a cycle, different instructions requiring different numbers of cycles or tasks other advantages => reuse of functional units (e.g., alu, memory) performance = instructions * cpi * cycle time
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CSE 141 Allan Snavely High-level View CSE 141 Allan Snavely Breaking Execution Into Clock Cycles We will have five execution steps (not all instructions use all five) – fetch – execute – memory access – write-back We will use Register-Transfer-Language (RTL) to describe these steps
Background image of page 2
CSE 141 Allan Snavely Breaking Execution Into Clock Cycles Introduces extra registers when: – signal is computed in one clock cycle and used in another, AND – the inputs to the functional block that outputs this signal can change before the signal is written into a state element. Significantly complicates control. Why? The goal is to balance the amount of work done each cycle. CSE 141 Allan Snavely Multicycle datapath
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CSE 141 Allan Snavely 1. Fetch IR = Mem[PC] PC = PC + 4 ( may not be final value of PC ) CSE 141 Allan Snavely 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) compute target before we know if it will be used (may not be branch, branch may not be taken)
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 18

L9 - Multiple Clock Cycle CPU or Breaking Up Is Hard To Do...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online