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l11redo - Designing a Pipelined CPU CSE 141 Allan Snavely...

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CSE 141 Allan Snavely Designing a Pipelined CPU CSE 141 Allan Snavely Review -- Single Cycle CPU PC Instruction memory Read address Instruction [31–0] Instruction [20 16] Instruction [25 21] Add Instruction [5 0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch RegDst ALUSrc Instruction [31 26] 4 16 32 Instruction [15 0] 0 0 M u x 0 1 Control Add ALU result M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend M u x 1 ALU result Zero PCSrc Data memory Write data Read data M u x 1 Instruction [15 11] ALU control Shift left 2 ALU Address
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CSE 141 Allan Snavely Review -- Multiple Cycle CPU Shift left 2 PC M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] M u x 0 1 M u x 0 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0] Instruction [31-26] Instruction [5–0] M u x 0 2 Jump address [31-0] Instruction [25–0] 26 28 Shift left 2 PC [31-28] 1 1 M u x 0 3 2 M u x 0 1 ALUOut Memory MemData Write data Address CSE 141 Allan Snavely Review -- Instruction Latencies Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Single-Cycle CPU Multiple Cycle CPU Ifetch Reg/Dec Exec Wr Add
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CSE 141 Allan Snavely Instruction Latencies and Throughput Single-Cycle CPU Multiple Cycle CPU Pipelined CPU Cyc le 1Cyc 2Cyc 3Cyc 4Cyc 5Cyc 6Cyc 7Cyc 8 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load 5 Ifetch Reg/Dec Exec Mem Wr Load Ifetch Reg/Dec Exec Mem Wr Load CSE 141 Allan Snavely Pipelining Advantages Higher maximum throughput Higher utilization of CPU resources But, more complicated datapath, more complex control (?)
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CSE 141 Allan Snavely Pipelining Advantages CPU Design Technology Single-Cycle CPU Multiple-Cycle CPU Pipelined CPU Control Logic Combinational Logic FSM or Microprogram Combinational Logic Peak Throughput 1 1 1 CSE 141 Allan Snavely Pipelining in Modern CPUs CPU Datapath Arithmetic Units System Buses Software (at multiple levels) etc. ..
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CSE 141 Allan Snavely A Pipelined Datapath IF: Instruction fetch ID: Instruction decode and register fetch
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This note was uploaded on 07/15/2011 for the course ECO 2023 taught by Professor Mr.raza during the Summer '10 term at FAU.

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l11redo - Designing a Pipelined CPU CSE 141 Allan Snavely...

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