# hw7_su08 - (b V in = 2.99 volts 3 A CMOS inverter...

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ECE 442 Electronic Circuits Homework 7 Due Friday July 11, 2008 1. Using PSpice , plot the output voltage of the clamping circuit shown for two cycles of input signal. What will the dc voltage of the output become after several input cycles? 30 μ s 1V -1V 0 V in C= 2 μ F V out 2. A CMOS inverter is powered by a 5-V supply. The following parameters are given: K n = μ WC ox /2L=30 A/V 2 for the NMOS and K p = WC ox /2L=30 A/V 2 for the PMOS. If V Tn =- V Tp =0.8 V, Using Pspice , find V out for (a) V in = 2.62 volts and
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Unformatted text preview: (b) V in = 2.99 volts. 3. A CMOS inverter fabricated in a process for which KP(nmos) = KP (pmos) = 270 μ A/V 2 , V tn =-V tp =0.7 V, and V DD = 3.3 V. The gate-drain overlap capacitance (CGDO) and effective drain-body capacitance (CBD) are 0.4 fF and 1.0 fF, respectively. A capacitance of 0.05 pF is placed at the load. Using Pspice , find t PLH , t PHL , and t P . Use a pulse with rise time TR = 1.1 ns and fall-time TF = 0.1 ns....
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## This note was uploaded on 09/07/2011 for the course ECE 442 taught by Professor Schutt-aine during the Summer '08 term at University of Illinois at Urbana–Champaign.

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