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Unformatted text preview: (b) V in = 2.99 volts. 3. A CMOS inverter fabricated in a process for which KP(nmos) = KP (pmos) = 270 A/V 2 , V tn =-V tp =0.7 V, and V DD = 3.3 V. The gate-drain overlap capacitance (CGDO) and effective drain-body capacitance (CBD) are 0.4 fF and 1.0 fF, respectively. A capacitance of 0.05 pF is placed at the load. Using Pspice , find t PLH , t PHL , and t P . Use a pulse with rise time TR = 1.1 ns and fall-time TF = 0.1 ns....
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- Summer '08