Lect_09 - ECE 442 SolidState Devices & Circuits 9....

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Jose E. Schutt Aine ECE 442 ECE 442 Solid 9. SPICE Jose E. Schutt-Aine University of Illinois jschutt@emlab.uiuc.edu
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Jose E. Schutt Aine ECE 442 * Schematic editor * Circuit level simulator * Layout editor * * Design rule checker * Netlist extractor * Layout vs Schematic * Libraries * Design verification * Electromagnetic analysis Tools for Physical Design Tools for Physical Design
Background image of page 2
3 Jose E. Schutt Aine ECE 442 Design Verification Behavior Design Behavior Synthesis RTL Synthesis Place and Route Custom Design RTL Design Layout Verif. Parasitic Extraction Floorplanning Functionality Timing Fab Design for Test Chip Test Module Reuse Spec. Hardware/Software Partitioning Arch. Analysis Customer Customer Analog/RF Design tight integration required Design Flow Design Flow
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Jose E. Schutt Aine ECE 442 ± Established platform ± Powerful engine ± Source code available for free
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/07/2011 for the course ECE 442 taught by Professor Schutt-aine during the Summer '08 term at University of Illinois at Urbana–Champaign.

Page1 / 12

Lect_09 - ECE 442 SolidState Devices & Circuits 9....

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online