# Lect_15 - ECE442 SolidStateDevices&Circuits...

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1 Jose E. Schutt Aine ECE 442 ECE 442 Solid State Devices & Circuits 15. Advanced Techniques Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois [email protected]

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2 Jose E. Schutt Aine ECE 442 Darlington Configuration - Popular BJT combination - Composite transistor with β = 1 2 - Can be used as the cascade of two CC
3 Jose E. Schutt Aine ECE 442 Darlington Voltage Follower ( ) ( )( ) 12 2 11 in e e E Rr r R ββ =+ + + + ( ) 2 2 /1 // 1 β ++ + es i g out E e rR RR r () 2 2 1 out E i g sig Ee v R v = + + +

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4 Jose E. Schutt Aine ECE 442 Darlington Voltage Follower Darlington follower presents high input impedance
5 Jose E. Schutt Aine ECE 442 Darlington Voltage Follower ( ) ( ) ( ) 12 2 11 in e e E Rr r R ββ =+ + + + 2 2 /( 1) // 1 β ⎡⎤ ++ ⎣⎦ + es i g out E e rR RR r 21 1 2 /( 1) /( E MB Ee e s i g R A = + + + Voltage gain: Output impedance Input impedance

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6 Jose E. Schutt Aine ECE 442 Concepts - Many op amps consist of 3 amplifying stages - The first stage is always a high-gain differential stage - The second stage has moderate value of voltage gain - The last stage is often a buffer stage with high current gain and voltage gain near unity - The high-frequency poles of each stage introduce phase shift at higher frequencies Î may lead to oscillations Op Amp Architecture
7 Jose E. Schutt Aine ECE 442 Specifications - Input Offset Voltage ( V os ) - Input Offset Voltage Drift ( TCV os ) - Input Bias Current ( I B ) - Input Offset Current ( I os ) - Common-Mode Input Voltage Range ( CMVR ) - Common-Mode Rejection Ratio ( CMRR ) - Power Supply Rejection Ratio ( PSRR ) Op Amp Specifications

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8 Jose E. Schutt Aine ECE 442 In the differential amplifier shown, Q 1 and Q 2 form the differential pair while the current source transistors Q 4 and Q 5 form the active loads for Q 1 and Q 2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q 1 and Q 2 is not shown. The following specifications are desired: differential gain A d = 80V/V, I REF = 100 μ A, the dc voltage at the gates of Q 6 and Q 3 is +1.5V; the dc voltage at the gates of Q 7 , Q 4 and Q 5 is –1.5V. CMOS OP Amp Example The technology available is specified as follows: μ n C ox =3 p C ox = 90 μ A/V 2 ; V tn =|V tp | =0.7V, V An =|V Ap | = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify I D and V GS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results.
9 Jose E. Schutt Aine ECE 442 CMOS OP Amp Example

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10 Jose E. Schutt Aine ECE 442 1.5 ( 1.5) 3 100 30 0.1 REF V I AR k Rm A μ − − == = = Ω Drain currents are determined by symmetry and inspection V GS values are also determined by inspection for all transistors except Q 1 and Q 2 . To determine V GS for Q 1 and Q 2 , we do the following: the equivalent load resistance will consist of r o1 in parallel with r o4 for Q 1 and r o2 in parallel with r o5 for Q 5 . Since the r o
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Lect_15 - ECE442 SolidStateDevices&Circuits...

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