Lect_16 - ECE ECE442 SolidStateDevices&Circuits...

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CE 442 ECE 442 Solid State Devices & Circuits 16. Review Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 Jose E. Schutt Aine ECE 442
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Diode Circuits - Rectification A t sin in VA ω = Rectification with ripple reduction. C must be large enough so that RC time constant is much larger than period 2 Jose E. Schutt Aine ECE 442
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Example Find the barrier voltage across the depletion region of a silicon diode at T = 300 K with N D =10 15 /cm 3 and N A =10 18 /cm 3 . N 2 ln A D oT i NN VV n ⎛⎞ = ⎜⎟ ⎝⎠ Use 0 3 @ 300K, 10 1. 51 0/ cm i n = × 0.026 V T V = () 18 15 13 2 20 10 10 10 0.026ln 0.026ln 2.25 1.5 10 oo V ψ ⎡⎤ == = × 0.026 29.12 0.7571 volts V = =×= 0.7571 volts V = = 3 Jose E. Schutt Aine ECE 442
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Example Two diodes are connected in series as shown in the figure with I s1 =10 -16 A and I s2 =10 -14 A. If the applied voltage is 1 V, calculate the currents I D1 and I D2 and the voltage across each diode V D1 and V D2 . 2 D VV The diode equations can be written as: 1 / 11 DT DS II e = 2 / 22 e = 12 1 1 1 DD T V S D SD I I e = = 1 ln 0.12 S D I V ⎛⎞ −= = ⎜⎟ from which 2 S I ⎝⎠ 1 + = 2 0.44 V D V = 1 0.56 V D V = 16 0.56/0.026 0 0 22 A= e I = Using KVL, we get from which and 4 Jose E. Schutt Aine ECE 442 10 0.22 A= D D Ie μ ==
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MOS – Triode Region - 1 () μ ⎡⎤ =− ⎣⎦ D ox GS T DS W IC V V V L C ox : gate oxide capacitance electron mobility ( ) ± DS GS T VV V : electron mobility L : channel length W : channel width threshold oltage 3.9 ε == ox o x C 5 Jose E. Schutt Aine ECE 442 V T : threshold voltage ox ox ox tt
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MOS – Triode Region - 2 () 2 1 μ =− D n ox GS T DS DS W IC V V V V > GS T VV 2 ⎣⎦ L ( ) <− D SG S T V – Charge distribution is nonuniform across channel – Less charge induced in proximity of drain 6 Jose E. Schutt Aine ECE 442
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MOS – Active Region Saturation occurs at pinch off when ( ) = −= DS GS T DSP VV V V V () 2 μ =− Dn o x G S T W IC V V DS GS T V >− > GS T aturation) 7 Jose E. Schutt Aine ECE 442 2 L (saturation)
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CMOS Logic Gate Circuits Two Networks – Pull-down network (PDN) with NMOS ull p network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors – Pull-up network (PUN) with PMOS PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices – In parallel to form OR functions series to form AND functions 8 Jose E. Schutt Aine ECE 442 – In series to form AND functions
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Pull-Down Networks YA B =+ B = 9 Jose E. Schutt Aine ECE 442
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Pull-Up Networks YA B =+ B = 10 Jose E. Schutt Aine ECE 442
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asic Basic Logic Function Basic Function INVERTER NOR NAND Symbol Devices 1 PMOS 2 PMOS-Series 2 PMOS-Parallel # Devices PUN 1 NMOS 2 NMOS-Parallel 2 NMOS-Series # Devices PDN Truth Table 11 Jose E. Schutt Aine ECE 442
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Pull-Down and Pull-Up Functions Pull-up network (PUN) Pull-down network (PDN) Key features – When PDN switch is on, PUN switch is off and vice versa – Conditions for being on and off are omplementary 12 Jose E. Schutt Aine ECE 442 complementary
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Lect_16 - ECE ECE442 SolidStateDevices&amp;Circuits...

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