EE40 Lecture 17 - Digital Power and Delay

EE40 Lecture 17 - Digital Power and Delay - EE40 Lecture 17...

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EE40 Lecture 17 Digital Circuits – Power and Delay Neel Shah 8/3/11
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Class Midterm 2 will be handed back today Grades will update on bSpace by Friday Final week office hours are different New: Thursday 8/11, 10 AM – 12 PM Your GSI office hours remain the same Last chance to pick up assignments: 8/10 in-class Last chance to submit extra credit: 8/10 in-class Guest lecture this Friday, 8/5 Email me topics ahead of time so I can prepare them
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Field Effect Transistor P is (effectively) a high resistance block of material, so current can barely flow from + to The n region is a reservoir of extra electrons (we will discuss the role of the n region later) When C is “on”, i.e. V C is relatively positive, then electrons from inside the P region collect at bottom of insulator, forming a “channel” + V C - - - - - - - - - - - - - (Drain) (Source) (Gate) + -
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Field Effect Transistor + V C • When the channel is present, then effective resistance of P region dramatically decreases • Thus: – When C is “off”, switch is open – When C is “on”, switch is closed - - - - - - - - - - - - - (Drain) (Source) (Gate) + -
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Field Effect Transistor + V C • If we apply a positive voltage to the plus side – Current begins to flow from + to – Channel on the + side is weakened - - - - - - (Drain) (Source) (Gate) + - + -
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The SR MOSFET Model The commonality with all these models is the switching nature Here we are switching a resistor on and off This is true for any switch – even mechanical switches have contact resistance!
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The SRC MOSFET Model The SRC model is just like the SR model but adds a capacitor to the gate input
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The SRC MOSFET Model Suppose we chain two inverters…
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This note was uploaded on 09/09/2011 for the course EECS 40 taught by Professor Chang-hasnain during the Summer '08 term at Berkeley.

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EE40 Lecture 17 - Digital Power and Delay - EE40 Lecture 17...

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