lec9-coherence

lec9-coherence - Cache Coherency in Multiprocessor Systems...

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Architecture of Parallel Computers Page 1 Cache Coherency in Multiprocessor Systems The Modified Exclusive Shared Invalid (MESI) algorithm for cache coherency. MESI State Definition Modified (M) The line is valid in the cache and in only this cache. The line is modified with respect to system memory—that is, the modified data in the line has not been written back to memory. Exclusive (E) The addressed line is in this cache only. The data in this line is consistent with system memory. Shared (S) The addressed line is valid in the cache and in at least one other cache. A shared line is always consistent with system memory. That is, the shared state is shared-unmodified; there is no shared-modified state. Invalid (I) This state indicates that the addressed line is not resident in the cache and/or any data contained is considered not useful. Note that: Exclusive may also be called CleanExclusive Modified may also be called DirtyExclusive Some processors add a fifth state for Shared Modified and call it the MOESI protocol. The caches with the shared modified state update each other’s lines with current data, but do not write it back to main memory. The five MOESI states are defined as: Exclusively Modified (M) Shared Modified (O) Exclusive Clean (E) Shared Clean (S) Invalid (I)
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© 1997, 1999, G.Q. Kenney CSC 506, Summer 1999 Page 2 Picture the MESI cache states: Valid Data Modified in Cache A M Cache A Invalid Data Cache B Invalid Data System Memory Valid Data Shared in Cache A S Cache A Valid Data Cache B Valid Data Valid Data Exclusive in Cache A E Cache A Invalid Data Cache B Valid Data Invalid Data Invalid in Cache A I Cache A Don't Care Cache B Don't Care S I System Memory System Memory System Memory
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Architecture of Parallel Computers Page 3 MESI State Diagram Invalid Shared Modified Exclusive RH SHR RH RH SHR WH SHI RME Read SHI RMS Read SHR Push WH Invalidate WM SHI Push WH LRU Push Invalidate Read Events: RH = Read Hit RMS = Read miss, shared RME = Read miss, exclusive WH = Write hit WM = Write miss SHR = Snoop hit on read SHI = Snoop hit on invalidate LRU = LRU replacement Bus Transactions: Push = Write cache line back to memory Invalidate = Broadcast invalidate Read = Read cache line from memory
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© 1997, 1999, G.Q. Kenney
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lec9-coherence - Cache Coherency in Multiprocessor Systems...

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