pram - COMP 203: Parallel and Distributed Computing PRAM...

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COMP 203: Parallel and Distributed Computing PRAM Algorithms Siddhartha Chatterjee Jan Prins Spring 2002 Contents 1 The PRAM model of computation 1 2 The Work-Time paradigm 3 2.1 Brent’s Theorem . . ........................................... 4 2.2 Designing good parallel algorithms . ................................... 6 3 Basic PRAM algorithm design techniques 6 3.1 Balanced trees . . . . ........................................... 6 3.2 Pointer jumping . 8 3.3 Algorithm cascading . .......................................... 11 3.4 Euler tours. ................................................ 12 3.5 Divide and conquer . ........................................... 13 3.6 Symmetry breaking . 15 4 A tour of data-parallel algorithms 17 4.1 Basic scan-based algorithms . ...................................... 17 4.2 Parallel lexical analysis. ......................................... 19 5 The relative power of PRAM models 19 5.1 The power of concurrent reads . ..................................... 20 5.2 The power of concurrent writes. 5.3 Quantifying the power of concurrent memory accesses . ........................ 21 5.4 Relating the PRAM model to practical parallel computation. ...................... 22 1 The PRAM model of computation In the first unit of the course, we will study parallel algorithms in the context of a model of parallel computation called the Parallel Random Access Machine (PRAM). As the name suggests, the PRAM model is an extension of the familiar RAM model of sequential computation that is used in algorithm analysis. We will use the synchronous PRAM which is defined as follows. 1. There are processors connected to a single shared memory. 2. Each processor has a unique index called the processor id . 3. A single program is executed in single-instruction stream, multiple-data stream (SIMD) fashion. Each instruc- tion in the instruction stream is carried out by all processors simultaneously and requires unit time, regardless of the number of processors.
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2 Copyright c Siddhartha Chatterjee, Jan Prins 1997–2002 4. Each processor has a private flag that controls whether it is active in the execution of an instruction. Inactive processors do not participate in the execution of instructions, except for instructions that reset the flag. The processor id can be used to distinguish processor behavior while executing the common program. For example, each processor can use its processor id to form a distinct address in the shared memory from which to read a value. A sequence of instructions can be conditionally executed by a subset of processors. The condition is evaluated by all processors and is used to set the private flags. Only active processors carry out the instructions that follow. At the end of the sequence the private flags are reset so that execution is resumed by all processors. The operation of a synchronous PRAM can result in simultaneous access by multiple processors to the same location in shared memory. There are several variants of our PRAM model, depending on whether such simultaneous access is permitted (concurrent access) or prohibited (exclusive access). As accesses can be reads or writes ,wehave the following four possibilities: 1. Exclusive Read Exclusive Write (EREW) : This PRAM variant does not allow any kind of simultaneous access to a single memory location. All correct programs for such a PRAM must insure that no two processors access a common memory location in the same time unit.
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This note was uploaded on 09/10/2011 for the course CS 6143 taught by Professor Hadimioglu during the Spring '10 term at NYU Poly.

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pram - COMP 203: Parallel and Distributed Computing PRAM...

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