FinalExample_EE3193

FinalExample_EE3193 - . "A ‘ = R ER 3193 —...

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Unformatted text preview: . "A ‘ = R ER 3193 — Intro. to VLSI _ 7 Name: C1 M P \Q Exam 2 ~— 4/24/07 You have the entire class to complete your work. This exam is closed book and closed notes. Some formulas are provided below that you may need to complete this exam. Unless other'wise specified, assume: C E Cox fl 0.623 1F; R = 34 k9 MOSFET I—V Relationships: 0 Vg: < V:_ CutOff I — V V ‘Vds V ' V I V - 4v ‘ E g: "" : ""” 2 ds d; < m. lmear “gawk: _' Vt? Va: Vzis'al ‘ saturation ‘ Summar of L0 ical Effort Notation ' Path Exression N I C CO“ a electrical effort h = m" ‘ H = "p m Cir: Cinmarh. ‘ I I. Can a + Co a r branching effort 5 m w B: H5,- onparh Good Luck! /5“"‘ 1. Complete the folléwing given the function F 2 AB + CDE . Impiement F as the foliowing and be sure to inciude transistor sizing 3. Static CMOS iogic gate. 2. Itnploment a 6T SRAM eel} and size the transistors for preper read and write operation. Also, describe the reasons for the sizes you choose. (You can start by sizing the inverter PDN NMOS transistors to 1600mm) 3. Draw transistor lav-61 schematics fer the following circuits. a. A high—level sensitive latch. if 4. You are given the following sequentiat circuit shown below. Estimate the delay through each combinational block to determine the combinationai propagation delay (th = tpdi ~l~ tpdz), Based on your findings, what is the minimum "clock period for this circuit to work correctly? {Assume rm : 100ps and the input capacitance ‘ of the latch Clam, = 20C) 51 ~<L~r\vt”°\-"~ 06H} * o E3 "\ i1 “ p i 03 "6‘ 5. Sketch a gate—level schematic 013 a 4ubit carry-ripple adder. Also draw transistor- Ievel schematics for all gates and logic blocks used. ...
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FinalExample_EE3193 - . &amp;quot;A ‘ = R ER 3193 —...

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