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Unformatted text preview: down. It may be reasonable to assume that clock speed doubles every 4 years: GHz f f year 119 ) 2015 ( 000 , 000 , 730 , 3 2 2 / ) 2005 ( GHz f f year 21 ) 2015 ( 000 , 000 , 730 , 3 2 4 / ) 2005 ( 2. (Problem 1.5 in text) Use a combination of CMOS gates (represented by their respective symbols) to implement the following functions from A, B, and C. 3. (Problem 1.3 in text) Sketch a transistor-level schematic for a CMOS 4-input NOR gate. 4. (Problem 1.11 in text) The figure below shows a stick diagram of a 2-input NAND gate. Sketch a cross-sectional view (side view) of the gate from X to X & ....
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
- Spring '10