{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

HW_EC - A& B = k 3 Design a 5:32 footed domino decoder...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EE3193/EL5473 ° Intro. to VLSI Extra Credit Homework Assignment Due December 11 by 5:00PM 1. (Problem 10.7 in text) Sketch the PG network for a modified 16-bit Slansky adder with fanout of [8, 1, 1, 1] rather than [8, 4, 2, 1]. Use buffers to prevent the less- significant bits from loading the critical path. Hint: You may need to sacrifice symmetry. 2. (Problem 10.12 in text) Sketch a design for a comparator computing
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: A & B = k . 3. Design a 5:32 footed domino decoder using domino AND gates. Indicate transistor sizes and estimate the delay of the decoder assuming it drives word lines each with a capacitance of C L = 20C. 4. (Problem 11.11 in text) Sketch a schematic for an 8-word x 2-bit NAND ROM that serves as a lookup table to implement a full adder....
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online