{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# HW3_1 - sized but also drives a total of 4 inverters(one in...

This preview shows page 1. Sign up to view the full content.

EE3193/EL5473 ° Intro. to VLSI Homework Assignment 3 Due beginning of class Tuesday, October 20 1. Sketch a 3-input AND-OR-INVERT (AOI) gate with transistor widths chosen to approximate the effective rise and fall resistances equal to a unit inverter. Compute the rising and falling propagation delays of the AOI gate driving h identical unit sized NOR gates using the Elmore delay model. Assume that every source/drain has fully contacted diffusion. 2. (Problem 4.6 in text) Let a 4x inverter have transistors four times as wide as those of a unit inverter. If a unit inverter has three units of input capacitance and parasitic delay of p inv , what is the input capacitance of the 4x inverter? What is the logical effort? What is the parasitic delay? 3. Consider a 7-stage ring-oscillator (7 inverters in a loop). Each inverter is unit
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: sized but also drives a total of 4 inverters (one in the oscillator and 3 off path). Using logical effort, estimate the clock period in units of & and the frequency f of the ring-oscillator. 4. (Problem 4.10 in text) Consider the two designs of a 2-input AND gate shown below. Give an intuitive argument about which will be faster. Back up your argument with a calculation of the path effort, delay, and input capacitances x and y to achieve this delay. 5. You are given the following multistage logic circuit built from static CMOS gates. Determine the sizing values for x and y that minimize the delay through the path from input A to output F . NOTE: Values written on gates represent the input capacitance of the respective gate. Assume load capacitance at F is 20C....
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online