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Unformatted text preview: sized but also drives a total of 4 inverters (one in the oscillator and 3 off path). Using logical effort, estimate the clock period in units of & and the frequency f of the ringoscillator. 4. (Problem 4.10 in text) Consider the two designs of a 2input AND gate shown below. Give an intuitive argument about which will be faster. Back up your argument with a calculation of the path effort, delay, and input capacitances x and y to achieve this delay. 5. You are given the following multistage logic circuit built from static CMOS gates. Determine the sizing values for x and y that minimize the delay through the path from input A to output F . NOTE: Values written on gates represent the input capacitance of the respective gate. Assume load capacitance at F is 20C....
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.
 Spring '10
 HalenLee
 Gate, Transistor

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