HW3Sol - EE3193/EL5473 Intro. to VLSI Homework Assignment 3...

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EE3193/EL5473 – Intro. to VLSI Homework Assignment 3 Solutions 1. Sketch a 3-input AND-OR-INVERT (AOI) gate with transistor widths chosen to approximate the effective rise and fall resistances equal to a unit inverter. Compute the rising and falling propagation delays of the AOI gate driving h identical unit sized NOR gates using the Elmore delay model. Assume that every source/drain has fully contacted diffusion. The rising delay is ( R /2)*12 C + R *(7 C +5 hC ) = (13+5 h ) RC , if both of the series pMOS transistors have their own contacted diffusion at the intermediate node. More realistically, the diffusion will be shared, reducing the delay to ( R /2)*8 C + R *(7 C +5 hC ) = (11+5 h ) RC . Neglecting the diffusion capacitance not on the path from Y to GND, the (worst case) falling delay is ( R /2)*2 C + R *(7 C +5 hC ) = (8+5 h ) RC . 2. (Problem 4.6 in text) Let a 4x inverter have transistors four times as wide as those of a unit inverter. If a unit inverter has three units of input capacitance and
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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HW3Sol - EE3193/EL5473 Intro. to VLSI Homework Assignment 3...

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