HW4 - Q delay of the flip-flop in terms of the latch timing...

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EE3193/EL5473 Intro. to VLSI Homework Assignment 4 Due beginning of class November 24 1. (Based on problem 6.21 in text, requires Cadence) Use Cadence to simulate a pseudo-nMOS inverter in which the pMOS transistor is half the width of the nMOS transistor. What are the rising, falling, and average logical efforts from hand calculations? What are t pd , t pdf , and t pdr from simulation? Compare. 2. (Problem 6.35 in text) Design a domino circuit to compute F = ( A + B )( C + D ) as fast as possible. Each input may present a maximum of 30 º of transistor width. The output must drive a load equivalent to 500 º of transistor width. Choose transistor sizes to achieve least delay and estimate this delay in . 3. (Problem 7.8 in text) Consider a flip-flop built from a pair of transparent latches using nonoverlapping clocks. Express the setup time, hold time, and clock-to-
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Unformatted text preview: Q delay of the flip-flop in terms of the latch timing parameters and t nonoverlap . 4. (Problem 7.9 in text) For the path in the figure below, determine which latches borrow time and if any setup time violations occur. Repeat for cycle times of 1200, 1000, and 800 ps. Assume there is zero clock skew and that the latch delays are accounted for in the propagation delay ˜ & s. a. ˜ 1 = 550 ps; ˜ 2 = 580 ps; ˜ 3 = 450 ps; ˜ 4 = 200 ps b. ˜ 1 = 300 ps; ˜ 2 = 600 ps; ˜ 3 = 400 ps; ˜ 4 = 550 ps 5. (Problem 10.1 in text) Design an 8-bit adder. The inputs may drive no more than 30 º of transistor width and the output must drive a 20/10 inverter. Simulate the adder and determine its delay. 6. (Problem 11.3 in text) Sketch designs for a 6:64 decoder with and without predecoding. Comment on the pros and cons of predecoding....
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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