HW4Sol - EE3193/EL5473 Intro. to VLSI Homework Assignment 4...

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EE3193/EL5473 Intro. to VLSI Homework Assignment 4 Solution 1. (Based on problem 6.21 in text, requires Cadence) Use Cadence to simulate a pseudo-nMOS inverter in which the pMOS transistor is half the width of the nMOS transistor. What are the rising, falling, and average logical efforts from hand calculations? What are t pd , t pdf , and t pdr from simulation? Compare. *** simulation *** 2. (Problem 6.35 in text) Design a domino circuit to compute F = ( A + B )( C + D ) as fast as possible. Each input may present a maximum of 30 º of transistor width. The output must drive a load equivalent to 500 º of transistor width. Choose transistor sizes to achieve least delay and estimate this delay in . H = 500 / 30 = 16.7. Consider a two stage design: OR-OR-AND-INVERT + HI- skew INV. For dynamic AOI22: g d = 2/3 and p = 5/3. G = 2/3 * 5/6 = 5/9. P = 5/3 + 5/6 = 5/2. F = GBH = 9.28. f = F 1/2 = 3.05. D = 2 f + P = 8.6 . The inverter size is 500 * (5/6) / 3.05 = 137. !" #$ #$ #$ #$ !!$ 3.
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HW4Sol - EE3193/EL5473 Intro. to VLSI Homework Assignment 4...

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