LabSession2_1

LabSession2_1 - where the minimum width is 600 nm. 2. Draw...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EE3193/EL5473 Intro. to VLSI Lab Session 2 Before starting the lab itself, complete Tutorial 2 and you may want the TA to check off that it has been completed successfully. ** Tutorials are found at: http://eeweb.poly.edu/labs/nanovlsi/tutorials/CustomICTut.htm 1. Create a 3-input NOR gate schematic in the EL5473 library and name the new cell view NOR3. ± NOTE : Make sure to size this gate based on the unit inverter created in tutorial 2
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: where the minimum width is 600 nm. 2. Draw the layout of the 3-input NOR gate using the techniques you learned in tutorial 2. 3. When you are finished, run DRC and make sure there are no errors. Select and copy the text in the icfb window verifying DRC ran with no errors. The schematic, layout, and DRC results are your deliverables....
View Full Document

Ask a homework question - tutors are online