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Unformatted text preview: Juuwr/ EE 3193 ~— Intro. to VLSI Name: 5 Q fa» Midterm Exam  3l13/87 You have the entire class to complete your work. This exam is closed book and closed
notes. Some fonnulas are provided beiow that you may need to complete this exam. Unless otherwise speciﬁed, assume: C *1 Cox = 0.625 fF; R = 34 kn \N MOSFET lV Relationships: I 0 Vgs < V} cutoff
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~ :2“: 4240 1. Complete the following given the function F 2 AB + Cl!) + E . S” a. Implement F as a static CMOS logic gate. Be sure to show transistor sizing. c. Sketch a layout of this circuit with sizes labeled accordingly.
.i. (Do not .1 bout desi u  (1. Estimate the delay of tie gate as a function of “c from logical effort. Assume
5,, the gate is loaded by an output capacitance equal to 10 2k widths. 2. Given the pass transistor circuits below, determine the voltage Vow (rightmost
node) for each. Assume Vm 2 V, and V,p = V,. V \ED Van Van DD VDD‘ I l l VE3€;;1__ V .wx/T r.
5" v” 3. You are given the following multistage logic circuit shown below. Estimate the
delay through the path indicated using path logical effort. You can assume the
numbers on the gates represent the input capacitance of the respective gate. rzja 4. The following 5—stage ring oscillator is implemented with unit sized static CMOS
inverters. Also notice that each stage is loaded by two inverters. Based on logical effort for delay estimation, what would the frequency of this oscillator be as a
ﬁmction of 1‘? WW Shel “2.5 .10 5. Design a full adder. Assume the inputs are A and B with carry in C1,, also
provided. The outputs of the circuit should be S for sum and Com for carry out
such that S = A + B + Cm (sum not OR). a. Design this adder at the gate Ievei. : AGE 3636s;
00139“ 2 A8 + Adan +§5Cm = 48+ (AQBBC‘A b. New extend your digital circuit to a 2—bit adder. (E.g., use 2 full adders
designed in (a) and connect CW, from the ﬁrst with Ci" of the second). so e. For the 2bit full adder designed in (b), show the circuit ievel schematics of all
gates used. Make sure you determine and show sizing of the transistors. (You may use any logic family you desire)
sl X a Q HAND gm pmwui’v's) The critical path of a logic circuit is the path between input and output with
longest delay. For your 2—bit full adder, identify the critical path and estimate
its delay in T. ...
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 Spring '10
 HalenLee
 Transistor, Logic gate, CMOS logic gate, static cmos, path logical effort

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