2007_1_Design of MIPS Processor supporting Mac with FPGA

2007_1_Design of MIPS Processor supporting Mac with FPGA -...

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- i - <Undergraduate Thesis: EEE-2007-01-48> Design of MIPS Processor Supporting MAC with FPGA Munju Lee, Taewoo Han School of Electrical and Electronic Engineering College of Engineering
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- ii - Yonsei University <Undergraduate Thesis: EEE-2007-01-48> Design of MIPS Processor Supporting MAC with FPGA Thesis Advisor: Yongserk Lee A thesis submitted in a partial fulfillment for the senior independent study's requirements June 2007 Munju Lee, Taewoo Han School of Electrical and Electronic Engineering
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- iii - College of Engineering Yonsei University 감사의 글 2006 년 두 학기 동안 저희에게 알찬 강의를 해주시고 , 졸업 연구까 지 지도해 주신 이용석 교수님께 가장 먼저 감사의 글을 올립니다 . 잠깐 방학동안 연구실에 들어가 있었지만 , 진심으로 맞아주신 연구 실 분들께도 감사의 마음을 전합니다 . 좀 더 나은 결과를 위해 매일 연구실을 나갔던 저희에게 좋은 연구여건을 만들어 주셨습니다 . 업 연구 담당 조교로서 큰 줄기를 잡는데 조언을 아끼지 않으셨던 전호윤 조교님께 감사의 말씀을 드립니다 . 그리고 처음 막상 아무 것도 할 수 없었을 때 , 구체적으로 도움 마다하지 않으셨던 원영 형 , 판기 형 정말 감사드립니다 . 두 학기 간 교과목 조교였던 현필 형 그리고 항상 옆에 계셔주셨던 형표 형 , 종수 형 , 재인이 형 , 지나가 면서 한 번 보시고 큰 문제점을 지적해 주셨던 용주 형님 , 하영이 , 이것저것 귀찮게 많이 물어봐도 항상 친절했던 동현 씨 , 그리고 은지 누나 , 재희 씨 , 상식 형 , 연구실 살림꾼 민영 씨 , 석한 씨 모든 연구실 분들께 감사의 마음을 전합니다 .
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- iv - Figure index iv Table index vi Abstract vii 1. Introduction 1 2. Backgrounds 2 2.1. MAC 2 2.1.1. A radix-4 modified Booth's algorithm 2 2.1.2. Sign or zero Extension 3 2.1.3. Wallace Tree 5 2.1.4. 4:2 carry save adder 5 2.1.5 Carry select adder 6 2.2. MIPS processor 7 2 .2 .1 . MIPS is the RISC processor 8 2.2.2. MIPS Instruction formats 9 2.2.3. Pipelining 10 2.2.4. Pipeline Hazards 11 3. Circuit Design Features 13 3.1. MAC 13 3.1.1. Block diagram of MAC 13 3.1.2. Block diagram of multiplier 14 3.1.3. Block diagram of an Accumulator 15 3.1.4. Signed or unsigned multiplication select mode 15 3.1.5. Booth encoder 15 3.1.6. Problem of the sign extension bits 16 3.1.7. Wallace tree with 4:2 CSA 19 3.2. MIPS processor 21 3.2.1. Instruction fetch 22 3.2.2. Instruction decode 22 3.2.3. Execute 23 3.2.4. Memory 23 3.2.5. Write back 23 3.2.6. Using a HDL to Describe and Modeling a MIPS processor 24 3.3 . MIPS with MAC 25 3.3.1 Special instruction MAC 25 3.3.2 Total diagram of designed MIPS with MAC 25 Contents
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- v - 4. Verification and System Analysis 27 4.1. MAC 27 4.1.1. Booth multiplier 27 4.1.2. Basic type MAC 28 4.1.3 Advanced MAC 30 4.2. MIPS processor 33 4.2.1. One instruction mul 33 4.2.2. Loop operation 33 4.3. MIPS with MAC 35 4.3.1. Use MAC as Booth multiplier 35 4.3.2. Use MAC as Multiplier and Accumulator 37 4.3.3. Compare the two methods of Matrix Calculating 38 5. Conclusion 39 5.1 What we know 39 5.2 A fall of system performance after connecting MAC to MIPS processor 39 5.3 Solution 40 6. Reference 44 국문요약 45
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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2007_1_Design of MIPS Processor supporting Mac with FPGA -...

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