00006637

00006637 - Parallel architecture modified Booth multiplier...

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Parallel architecture modified Booth multiplier A.R. Cooper, MSc, PhD Indexing terms: Circuit theory and design, Array processing, Digital arithmetic, Algorithms Abstract: The paper describes a novel implemen- tation of the modified Booth algorithm in which groups of the partial product terms are summed in parallel and these partial results are then com- bined in a Wallace tree adder array. The final output is formed by an accelerated carry adder. An extension of the scheme from unsigned binary arithmetic to 2’s complement is also described. A 16-bit version of the architecture has been model- led in Pascal and Ella to validate its operation for use in a systolic array DSP chip. 1 Introduction An increasing number of high-speed DSP applications have need of a high-precision (16 bits or more) fixed- or floating-point multiplier suitable for VLSI implementa- tion. The modified Booth algorithm is a common approach to the VLSI implementation of this require- ment. Modified Booth partial products are convention- ally added one at a time in an adder array whose result is formed in a final carry propagate added stage. This paper describes a novel architecture for a modified Booth multiplier that uses increased parallelism to reduce the number of gate delays through it [ 13. As multipliers are a critical aspect of any DSP chip development, there are several references in the literature to their VLSI implementation. Waser [2] gives a review of shift-and-add, Wallace tree and Booth’s algorithm architectures. Takeda et a1 [3] describe the design of a floating point processor where the critical path through the Booth array is twice as long as that through other functional blocks. They surmount this problem by pipe- lining their machine, thus also increasing throughput. Henlin al [4] use pipelining by inserting a single pipe- line register before the final carry-propagate adder of their Booth multiplier as the time to perform the final carry-propagate addition of the result can amount to half of the total multiplication time. Uya et al. [SI use a carry-select adder for the final propagate stage of their 32-bit Booth multiplier. In this, there is a tradeoff between high speed and silicon area; the carry-select adder is a very fast but large circuit. 2 Example of Booth’s algorithm In the shift-and-add form of multiplication the multi- plicand is added to the partial product at each bit posi- tion where a ‘1’ occurs in the multiplier operand. The Paper 60536 (ElO), first received 1st September 1987 and in modified form 29th February 1988 The author is with STC Technology Ltd., London Road, Harlow, Essex CM 17 9NA, United Kingdom IEE PROCEEDINGS, Vol. 135, Pt. G, No. 3, JUNE 1988 number of terms to be added is halved in the modified Booth recoding scheme by comparing every other bit of the multiplier operand with the next and previous bits and using this 3-bit code to determine which operation to perform. The operations, which are tabulated in Refer- ence 2, are: add once (001, OlO), add twice (01 l), subtract once (101, 110), subtract twice (loo), or do nothing
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00006637 - Parallel architecture modified Booth multiplier...

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