679267 - VLSI Design, 2002 Vol. 14 (4), pp. 315327 A Fast...

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A Fast ALU Design in CMOS for Low Voltage Operation A. SRIVASTAVA* and D. GOVINDARAJAN Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803-5901, USA (Received 6 October 2000; Revised 25 April 2001) A high-speed 4-bit ALU has been designed for 1 Voperation to demonstrate the usefulness of the back- gate forward substrate bias (BGFSB) method in 1.2 m m N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to j 0.4 j V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design. Keywords : ALU; Ripple carry adder; Low-voltage; Back-gate bias; Low power CMOS INTRODUCTION Digital integrated circuits commonly use CMOS circuits as building blocks. The continuing decrease in feature size of CMOS circuits and corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1,2]. Excessive power dissipation in integrated circuits, not only discourages their use in portable environment but also causes over heating, reduces chip life and degrades performance. Minimizing power dissipation is therefore important, both for increasing levels of integration and to improve reliability, feasibility and cost [3]. Different power reducing techniques such as reducing voltage, load capacitance or switching frequency of the output node, are being used to design low power, high-performance chips based on CMOS. At a given clock rate and for a known load capacitance, the dynamic power dissipation is proportional to the square of the power supply voltage [4]. Therefore, reducing the power supply voltage results in quadratic improvement in the power dissipation of a CMOS circuit, which is the most common and effective way of reducing the power consumption [5]. However, lowering the supply voltage causes two design problems. One problem is that the chip throughput is degraded due to increased circuit delays at reduced voltage [6]. The other problem is that there is a significant loss in the performance as the supply voltage reaches the sum of the thresholds of the PMOS and NMOS transistor [6]. Recently, it has been shown that low-threshold voltage devices can be used whenever high performance is required [7–9]. The threshold voltage can be reduced by the back-gate forward substrate bias (BGFSB) method for low-voltage digital circuit design [10]. This method reduces the threshold voltage of the P-MOSFET and the N-MOSFET and thus leads to reduced circuit delays and power. This method is suitable for the supply voltage between 0.6 and 1.5 V. In the other approach, several voltages are used on board to selectively bias different transistors [6]. The problem with this method is that the optimal voltages may vary on the chip at various
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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679267 - VLSI Design, 2002 Vol. 14 (4), pp. 315327 A Fast...

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