00746672

00746672 - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII:...

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Unformatted text preview: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 12, DECEMBER 1998 1585 Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers Yun-Nan Chang, Student Member, IEEE , Janardhan H. Satyanarayana, Member, IEEE , and Keshab K. Parhi, Fellow, IEEE Abstract Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial architectures ob- tained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial architectures is presented based on a novel design methodology. This methodology permits bit-level pipelining of the digit-serial architectures by moving all feedback loops to the last stage of the design. This enables bit-level pipelining of digit-serial architectures, thereby achieving sample speeds close to corresponding bit-parallel multipliers with lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The proposed approach is applied to the design of various multipliers which form the backbone of digital signal processing computations. The results show that for transformed multipliers with smaller digit sizes ( 4), the singly-redundant multiplier consumes the least power, and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit size for least power consumption in type-I and type-III multipliers is p P , where represents the word length. Among the bit-level pipelined digit-serial multipliers, it is found that the redundant multiplier offers the best choice in terms of both latency and power consumption. The proposed digit-serial multipliers consume on average 20% lower power than the traditional digit-serial architectures for the nonpipelined case and about 515 times lower power for the bit-level pipelined case. Also, modified Booth recoding is applied to transformed multipliers, and it is found that the recoded multipliers consume about 22% lower power than the transformed multipliers without recoding. Index Terms Bit-level pipelining, Booth recoding, carry-save arithmetic, digit-serial multiplier, low power, redundant arith- metic. I. INTRODUCTION D IGITAL signal processing (DSP) is used in a wide range of applications such as telephone, radio, video, sonar, etc. The sample rate requirements vary from application to application and can range anywhere from 10 kHz to 100 MHz. Manuscript received May 19, 1997; revised July 13, 1998. This work was supported by Defense Advanced Research Project Agency under Contract DA/DABT63-96-C-0050. This paper was recommended by Associate Editor T. Q. Nguyen....
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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00746672 - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII:...

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