01277450 - A High-Performance 32-bit Parallel Multiplier...

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A High-Performance 32-bit Parallel Multiplier Using Modified Booth's Algorithm and Sign-Deduction Algorithm Na TANG I. *, Jian-Hui nANG ' and Kenneth LIN I 'Research and Development Center of CZSI Circuits, Tongji Universir), Shanghai 200092, P R. Chino 'Departnienr of Coinputer Science and Technolog): Ton@ Universir), Shanghai 200092, P R. China Abstract A. high-perfonnance 32-bit parallel multiplier is proposed in this paper. A modified Booth's algorithm is used to unify signediiuisigned numbers operation and a new sign-deduction algorithm is used to eliminatc the sign bits array of pnrtial products. T!us niultiplier is used ui a 4OOMHz hgh perfominnce and full-custom designed 32-bit embedded iiiicroprocessor compatible withMIPS 32 4 KCT" developed by us. 1 Introduction In recent years, microprocessor-based systenis present fast-groning demand of embedded microprocessors with high speed and low power features. As a result, the multiplier, an important unit of embedded microprocessor, must meet these goals. Currently, there are two basic approaches to enhaiice the speed of a multiplier, one is the Booth algaritluii and the other is Wallace tree compressor or counter. However. both of them will lead to excessive energy dissipation [I]. When only Wallace tree is used to compress the nuniber of partial products of multiplier, the niultiplier array beconies veri/ large due to the large number of gates and the interconnect wires [Z, 31. It leads to !ugh-energy dissipation On the other hand, if the' standard Booth algorithm is used, the signe&unsigned iiiultiply is not unified [4] This paper preseuts a modified Booth algorithm to unify the siguediunsigned iiiultiply. Considering the instruction pipeline and chip area, a 32x32 multiplication is divided into two steps and is implemented by a %row 33-bit wide carry save adder (CSA) [j]. A new sign-deduction (SD) algorithm is employed to eliminate unnecessaIy hardware by using sign extension hits. ZAlgorithm Multiplication Bit-pair Bwth algorithm We adopt bit-pair Booth algo,:ithhm. The reasons are: (I) it does not have to distinguish the sign of operands. The multiplicand and iiiultiplier are represented by two's complement, the sign hit participating in operation; (2) bit-pair multiplication can reduce half of operation steps, thus it improves the speed. Multiplication is a multiply and addition iteration procedure. The bit-pair Booth algorithi is based on partitioning the multiplier into overlapping groups of 3 bits. We call them determination bits. Each group of deteniiination bits is then cncoded to generate a correct partial product. A 32x32 multiplication has 16 partial products shifted left 2 bits one after another. The addition result of the 16 partial products is the ultimate 64-bit product.
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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01277450 - A High-Performance 32-bit Parallel Multiplier...

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