01354130 - The 47th IEEE Symposium on Circuits and Systems...

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The 47th IEEE International Midwest Symposium on Circuits and Systems Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations of Signed Radix-4 Architectures Leonard0 L.de Oliveira Eduardo Costa UFSWPPGEE - Santa Maria, Brazil Jo50 Baptista UFSWPPGEE - Santa Maria, Brazil [email protected] br UCPel, Pelotas, Brazil [email protected] br [email protected] Sergio Bampi UFRGS,P. Alegre,Brazil [email protected] JosC Monteiro IST/INESC,Lisboa,Portugal [email protected] Abstract- In this paper, we describe the fully automated custom layout implementations of two architectures for signed multiplication. Performance comparisons between the two, namely in terms of their power consumption and area estimation are provided for 8 and 16-bit operands. The first architecture consists of a signed array multiplier that uses a radix-4 hybrid encoding to reduce the partial product lines and switching activity in the data buses. This new arithmetic operand encoding was recently proposed in [4], however only results at the logic level were presented. The second architecture implemented was the widely used modified Booth multiplier [SI. The layout of both multipliers was generated by an automatic layout synthesis tool called TROPIC [lo]. We compare the layout implementations in terms of area and power, as well as provide comparisons to first-order area estimates done in the logic design phase. The results show that the new hybrid array multiplier can be significantly more efficient, with close to 30% power savings. I. INTRODUCTION Multiplier modules are common to many DSP applications. The fastest types of multipliers are parallel multipliers. Among these, the Wallace multiplier [13] is among the fastest. However, they do not have such a regular structure as the conventional array [8] or Booth [9] multipliers. Hence, when layout regularity, high-performance and low power are primary concerns, Booth multipliers tend to be the primary choice [2], [5], [7], [9], [ 111. In this paper, we present layout implementations for both the Modified Booth multiplier and the new array multiplier using hybrid code proposed in [4]. We synthesize the multipliers by using an automatic synthesis tool named Tropic [IO]. In order to compare the Modified Booth and the hybrid array architectures, both using radix-4, the ELDO which is a spice-like simulator and is part of the Mentor Graphics environment, was used. The results show that the new array multiplier is significantly more efficient, saving more than 30% in power consumption. The power reduction presented by the new array multiplier is mainly due to the lower logic depth, which has a large impact in the amount of glitching in the circuit. We should stress further that, in contrast to the architecture presented in [4], increasing the radix for the Booth architecture is a difficult task, thus not being able to leverage from the potential savings of higher radices. This paper is organized as follows. The next section
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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01354130 - The 47th IEEE Symposium on Circuits and Systems...

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