The 2004 IEEE AsiaPacific Conference on
Circuits
and
Systems, December 69,2004
Design
of
a
Novel
Radix4
Booth
Multiplier
HsinLei Lin, Robert
C.
Chang, MingTsai Chan
Departmenf of Electrical Engineering,
National Chung Hsing University, Taichung, Taiwan
ABSTRACT
This paper presents a novel radix4 Booth multiplier. A
conventional
Booth multiplier consists of the Booth
encoder, the partialproduct summation tree, and the cany
propagate
adder. Different schemes are addressed to
improve the area and circuit speed effectively. A novel
modified Booth encodeddecoder is proposed
and the
summation column is compressed by the proposed MFAr.
The proposed design is simulated by Synopsys and Apollo.
It results 20% area reduction, 17%&24% power decrease,
and
15%
reduction of the delay time of the critical path.
1.
INTRODUCTION
The multiplier using the Booth algorithm is a wellknow
technique for highspeed and lowcost multipliers. There
are many researches on highspeed Booth multipliers, and
the main technique is the radix4 Booth encode[l6].
Although radix4 Booth can reduce the input bits and the
output bits to half, it also increases the time of compression.
In order to get a better system performance, we have
improved the circuit of the radix4 Booth multiplier in this
paper.
In the CPU and DSP processor design, we
use
the
modified multiplier scheme widely and commonly. There
are several types of multiplier such as series, parallel, array,
and encoding. The property of these multipliers as we
know that the series multiplier is the simplest
structure,
the
parallel scheme is higherspeed, the matrix one is more
difficult when it is used on symbol operation, and the
encoding one is much more efficient when it is used on
symbol operation. Therefore we modify the encoder and
the decoder in order to reduce area and increase the whole
speed.
This paper is organized as follows. Section I1 discusses the
proposed radix4 Booth multiplier which this paper is
proposed. Section I11 compares the proposed radix4 Booth
multiplier structure with a standard one. Section IV is the
conclusion.
2.
Radix4 Booth Multiplier
In this section, we present a novel scheme using the
modified
Booth encoderidecoder (MBE) and the re
modified fulladder (MFAr). It is improved from the Yen's
MBE [I] and the original 4to2 compressor to reduce the
critical path and area. Figure 1 shows the proposed radix4
Booth
multiplier, which consists of the 3bit Booth
encoder/decoders,
the
compressors,
and
the
carry
propagate adder [7111. The Booth encoder/decoder is the
first part of the multiplier when we
start
to calculate the
value of multiplicand and multiplicator.
Instead of the
partialproduct
summation
tree
(PPST),
the
Booth
encoder/decoder makes the calculation faster. The radix4
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 Spring '10
 HalenLee
 Electrical Engineering, Multiplication, The Circuit, Circuit complexity, compressor, Booth's multiplication algorithm, radix4 booth

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