01413009

01413009 - The 2004 IEEE Asia-Pacific Conference on...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9,2004 Design of a Novel Radix-4 Booth Multiplier Hsin-Lei Lin, Robert C. Chang, Ming-Tsai Chan Departmenf of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan ABSTRACT This paper presents a novel radix-4 Booth multiplier. A conventional Booth multiplier consists of the Booth encoder, the partial-product summation tree, and the cany- propagate adder. Different schemes are addressed to improve the area and circuit speed effectively. A novel modified Booth encodeddecoder is proposed and the summation column is compressed by the proposed MFAr. The proposed design is simulated by Synopsys and Apollo. It results 20% area reduction, 17%&-24% power decrease, and 15% reduction of the delay time of the critical path. 1. INTRODUCTION The multiplier using the Booth algorithm is a well-know technique for high-speed and low-cost multipliers. There are many researches on high-speed Booth multipliers, and the main technique is the radix-4 Booth encode[l-6]. Although radix-4 Booth can reduce the input bits and the output bits to half, it also increases the time of compression. In order to get a better system performance, we have improved the circuit of the radix-4 Booth multiplier in this paper. In the CPU and DSP processor design, we use the modified multiplier scheme widely and commonly. There are several types of multiplier such as series, parallel, array, and encoding. The property of these multipliers as we know that the series multiplier is the simplest structure, the parallel scheme is higher-speed, the matrix one is more difficult when it is used on symbol operation, and the encoding one is much more efficient when it is used on symbol operation. Therefore we modify the encoder and the decoder in order to reduce area and increase the whole speed. This paper is organized as follows. Section I1 discusses the proposed radix-4 Booth multiplier which this paper is proposed. Section I11 compares the proposed radix-4 Booth multiplier structure with a standard one. Section IV is the conclusion. 2. Radix-4 Booth Multiplier In this section, we present a novel scheme using the modified Booth encoderidecoder (MBE) and the re- modified full-adder (MFAr). It is improved from the Yen's MBE [I] and the original 4-to-2 compressor to reduce the critical path and area. Figure 1 shows the proposed radix-4 Booth multiplier, which consists of the 3-bit Booth encoder/decoders, the compressors, and the carry- propagate adder [7-111. The Booth encoder/decoder is the first part of the multiplier when we start to calculate the value of multiplicand and multiplicator. Instead of the partial-product summation tree (PPST), the Booth encoder/decoder makes the calculation faster. The radix-4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 4

01413009 - The 2004 IEEE Asia-Pacific Conference on...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online