An Efficient Modified Booth Multiplier
Architecture
Razaidi Hussin
1
, Ali Yeon Md. Shakaff
2
, Norina Idris
1
, Zaliman Sauli
1
, Rizalafande Che Ismail
1
and Afzan Kamarudin
1
2
School of Computer and Communication Engineering.
1
School of Microelectronic Engineering,
Universiti Malaysia Perlis (UniMAP),
P.O Box 77, d/a Pejabat Pos Besar,
01007 Kangar Perlis, Malaysia
shidee@unimap.edu.my
Abstract
in this paper, we present the design of an efficient
multiplication unit. This multiplier architecture is based on
Radix
4
Booth
multiplier.
In
order
to
improve
his
architecture, we have made 2 enhancements. The first is to
modify the Wen-Chang’s Modified Booth Encoder (MBE)
since it is the fastest scheme to generate a partial product.
However, when implementing this MBE with the Simplified
Sign Extension (SSE) method, the multiplication’s output is
incorrect. The 2
nd
part is to improve the delay in the 4:2
compressor circuit. The redesigned 4:2 compressor reduced
the delay of the Carry signal. This modification has been
made by rearranging the Boolean equation of the Carry
signal. This architecture has been designed using Quartus
II. The Gajski rule has been adopted in order to estimate
the delay and size of the circuit. The total transistor count
for this new multiplier is being a slightly bigger. This is due
to the new MBE which is uses more transistor. However in
performance speed, this efficiency multiplier is quite good.
The propagation delay is reduced by about 2% – 7% from
other designers.
I INTRODUCTION
With the constant growth of computer applications
such
as
computer
graphics
and
signal
processing,
fast
arithmetic
unit
especially
multipliers
are
becoming
increasingly important. Advanced VLSI technology has given
designer the freedom to integrate many complex components,
which was not possible in the past. Various high speed
multipliers have been proposed and realized [1, 2, 3, 5, 10, 11,
and 12].
There are 2 operations in implementing a Modified
Booth Multiplier design, which a generating the partial product
and accumulating the entire partial product. In producing
partial product the Booth Encoder and Booth Selector circuits
are used. Accumulation of the partial product is done by the
adder or compressor circuit. Ideally, the performance and size
of the multiplier circuit are dependent on these two operations.
The BE can be designed in many ways and the design will be
tradeoff between area and speed. The BE which has a better
performance in speed will be used in our design since the
objective is developing the fast multiplier. However, this BE
will create a problem when implementing the SSE method.
In the accumulation part, all partial products must be
accumulated to obtain the final result. A fast multi-operand
adder such as the Wallace tree [4] or the carry save adder
(CSA) tree using multi input counter and Compressor [5,6]
should be employed
for high speed accumulation. In this paper
we evaluate Booth encoding with respect to the use of 4:2