alu.eg1 - ECEN 4243 Computer Architecture A 32-Bit ALU...

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ECEN 4243 Computer Architecture A 32-Bit ALU Design Example January 23, 2001 page 1 of 10 A 32-Bit ALU Design Example A typical 32 bit ALU might look something like where the “d” output implements the function of “a” and “b” selected by the “S” control inputs. Note that the ALU is purely combinational logic and contains no registers and latches. The arithmetic functions are much more complex to implement than the logic functions. Consider the circuitry needed to implement d <= a xor b ab Cin Cout 32 32 32 V S 3 ALU d a(31) b(31) a(30) b(30) a(0) b(0) d(31) d(30) d(0) . . .
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ECEN 4243 Computer Architecture A 32-Bit ALU Design Example January 23, 2001 page 2 of 10 Contrast this with the circuit for the parallel adder. The xor operation requires the signals to travel through only one gate whereas the parallel adder circuit requires, in the worst case, the signal to travel through all 32 single bit adders. This has two significant consequences. 1. The worst case delay for the ALU is determined by the carry chain in the adder. 2. The synthesizer will spend a great deal of time trying to optimize (reduce the delay) of the carry chain for long carry chains. This is why it is impractical to synthesize all 32 bits at once. Fast Adder Design. The design of high speed carry chains is beyond the scope of this course (take the VLSI course). We will approximate the performance of a high speed carry chain with the following Manchester Carry Chain circuit. where the carry generate, g, and carry propagate, p, functions are defined as follows. g(i) <= a(i) and b(i) p(i) <= a(i) xor b(i) FA c(30) Cout a(30) b(30) a(31) b(31) a(0) b(0) Cin c(0) c(29) d(0) d(30) d(31) Cout p(31) p(31) g(31) c(31) p(30) Cin p(0) c(1) g(30) g(0) . . . p(30) p(0)
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ECEN 4243 Computer Architecture A 32-Bit ALU Design Example January 23, 2001 page 3 of 10 The transmission gate is a controllable switch as the following table indicates. The Z stands for a high impedance (open switch) output. Note: the delay predicted by the simulator for the transmission gate circuit is unrealisti- cally short and more sophisticated techniques are really used. When the Manchester carry chain is used, the adder circuit becomes Notice that the worst case delay is no longer through the adder cell and we can write a simple behavioral model to use with the synthesizer.
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This note was uploaded on 09/09/2011 for the course EE 3193 taught by Professor Halenlee during the Spring '10 term at NYU Poly.

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alu.eg1 - ECEN 4243 Computer Architecture A 32-Bit ALU...

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